mirror of
https://github.com/InoriRus/Kyty.git
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PS5 graphics (#42)
This commit is contained in:
InoriRus
@@ -120,19 +120,35 @@ constexpr uint32_t DB_RENDER_CONTROL_COPY_SAMPLE_MASK = 0xF;
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constexpr uint32_t DB_COUNT_CONTROL = 0x1;
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constexpr uint32_t DB_DEPTH_VIEW = 0x2;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_MASK = 0x7FF;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_SHIFT = 13;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_MASK = 0x7FF;
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constexpr uint32_t DB_DEPTH_VIEW = 0x2;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_MASK = 0x7FF;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_HI_SHIFT = 11;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_HI_MASK = 0x3;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_SHIFT = 13;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_MASK = 0x7FF;
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constexpr uint32_t DB_DEPTH_VIEW_Z_READ_ONLY_SHIFT = 24;
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constexpr uint32_t DB_DEPTH_VIEW_Z_READ_ONLY_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_VIEW_STENCIL_READ_ONLY_SHIFT = 25;
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constexpr uint32_t DB_DEPTH_VIEW_STENCIL_READ_ONLY_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_VIEW_MIPID_SHIFT = 26;
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constexpr uint32_t DB_DEPTH_VIEW_MIPID_MASK = 0xF;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_HI_SHIFT = 30;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_HI_MASK = 0x3;
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constexpr uint32_t DB_RENDER_OVERRIDE = 0x3;
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constexpr uint32_t DB_RENDER_OVERRIDE2 = 0x4;
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constexpr uint32_t DB_HTILE_DATA_BASE = 0x5;
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constexpr uint32_t PS_SHADER_SAMPLE_EXCLUSION_MASK = 0x6;
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constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
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constexpr uint32_t DB_DEPTH_BOUNDS_MIN = 0x8;
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constexpr uint32_t DB_DEPTH_BOUNDS_MAX = 0x9;
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constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
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constexpr uint32_t DB_DEPTH_SIZE_XY_X_MAX_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_SIZE_XY_X_MAX_MASK = 0x3FFF;
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constexpr uint32_t DB_DEPTH_SIZE_XY_Y_MAX_SHIFT = 16;
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constexpr uint32_t DB_DEPTH_SIZE_XY_Y_MAX_MASK = 0x3FFF;
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constexpr uint32_t DB_DEPTH_BOUNDS_MIN = 0x8;
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constexpr uint32_t DB_DEPTH_BOUNDS_MAX = 0x9;
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constexpr uint32_t DB_STENCIL_CLEAR = 0xA;
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constexpr uint32_t DB_STENCIL_CLEAR_CLEAR_SHIFT = 0;
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@@ -172,23 +188,41 @@ constexpr uint32_t DB_DEPTH_INFO_MACRO_TILE_ASPECT_MASK = 0x3;
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constexpr uint32_t DB_DEPTH_INFO_NUM_BANKS_SHIFT = 19;
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constexpr uint32_t DB_DEPTH_INFO_NUM_BANKS_MASK = 0x3;
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constexpr uint32_t DB_Z_INFO = 0x10;
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constexpr uint32_t DB_Z_INFO_FORMAT_SHIFT = 0;
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constexpr uint32_t DB_Z_INFO_FORMAT_MASK = 0x3;
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constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_SHIFT = 2;
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constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_MASK = 0x3;
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constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_SHIFT = 20;
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constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_MASK = 0x7;
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constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_SHIFT = 29;
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constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_SHIFT = 31;
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constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_MASK = 0x1;
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constexpr uint32_t DB_Z_INFO = 0x10;
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constexpr uint32_t DB_Z_INFO_FORMAT_SHIFT = 0;
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constexpr uint32_t DB_Z_INFO_FORMAT_MASK = 0x3;
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constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_SHIFT = 2;
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constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_MASK = 0x3;
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constexpr uint32_t DB_Z_INFO_ITERATE_FLUSH_SHIFT = 11;
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constexpr uint32_t DB_Z_INFO_ITERATE_FLUSH_MASK = 0x1;
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constexpr uint32_t DB_Z_INFO_PARTIALLY_RESIDENT_SHIFT = 12;
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constexpr uint32_t DB_Z_INFO_PARTIALLY_RESIDENT_MASK = 0x1;
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constexpr uint32_t DB_Z_INFO_MAXMIP_SHIFT = 16;
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constexpr uint32_t DB_Z_INFO_MAXMIP_MASK = 0xF;
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constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_SHIFT = 20;
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constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_MASK = 0x7;
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constexpr uint32_t DB_Z_INFO_DECOMPRESS_ON_N_ZPLANES_SHIFT = 23;
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constexpr uint32_t DB_Z_INFO_DECOMPRESS_ON_N_ZPLANES_MASK = 0xF;
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constexpr uint32_t DB_Z_INFO_ALLOW_EXPCLEAR_SHIFT = 27;
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constexpr uint32_t DB_Z_INFO_ALLOW_EXPCLEAR_MASK = 0x1;
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constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_SHIFT = 29;
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constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_SHIFT = 31;
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constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_MASK = 0x1;
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constexpr uint32_t DB_STENCIL_INFO = 0x11;
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constexpr uint32_t DB_STENCIL_INFO_FORMAT_SHIFT = 0;
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constexpr uint32_t DB_STENCIL_INFO_FORMAT_MASK = 0x1;
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constexpr uint32_t DB_STENCIL_INFO_ITERATE_FLUSH_SHIFT = 11;
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constexpr uint32_t DB_STENCIL_INFO_ITERATE_FLUSH_MASK = 0x1;
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constexpr uint32_t DB_STENCIL_INFO_PARTIALLY_RESIDENT_SHIFT = 12;
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constexpr uint32_t DB_STENCIL_INFO_PARTIALLY_RESIDENT_MASK = 0x1;
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constexpr uint32_t DB_STENCIL_INFO_RESERVED_FIELD_1_SHIFT = 13;
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constexpr uint32_t DB_STENCIL_INFO_RESERVED_FIELD_1_MASK = 0x7;
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constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_SHIFT = 20;
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constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_MASK = 0x7;
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constexpr uint32_t DB_STENCIL_INFO_ALLOW_EXPCLEAR_SHIFT = 27;
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constexpr uint32_t DB_STENCIL_INFO_ALLOW_EXPCLEAR_MASK = 0x1;
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constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_SHIFT = 29;
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constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_MASK = 0x1;
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@@ -245,21 +279,37 @@ constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_X_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_SHIFT = 16;
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constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL = 0x94;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR = 0x95;
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constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
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constexpr uint32_t PA_SC_VPORT_ZMAX_0 = 0xB5;
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constexpr uint32_t PA_SC_RIGHT_VERT_GRID = 0xE8;
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constexpr uint32_t PA_SC_LEFT_VERT_GRID = 0xE9;
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constexpr uint32_t PA_SC_HORIZ_GRID = 0xEA;
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constexpr uint32_t PA_SC_FOV_WINDOW_LR = 0xEB;
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constexpr uint32_t PA_SC_FOV_WINDOW_TB = 0xEC;
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constexpr uint32_t CB_RMI_GL2_CACHE_CONTROL = 0x104;
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constexpr uint32_t CB_BLEND_RED = 0x105;
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constexpr uint32_t CB_BLEND_GREEN = 0x106;
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constexpr uint32_t CB_BLEND_BLUE = 0x107;
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constexpr uint32_t CB_BLEND_ALPHA = 0x108;
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constexpr uint32_t CB_DCC_CONTROL = 0x109;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL = 0x94;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_X_SHIFT = 0;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_X_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_Y_SHIFT = 16;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_Y_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_WINDOW_OFFSET_DISABLE_SHIFT = 31;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_WINDOW_OFFSET_DISABLE_MASK = 0x1;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR = 0x95;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_X_SHIFT = 0;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_X_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_Y_SHIFT = 16;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_Y_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_15_TL = 0xB2;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_15_BR = 0xB3;
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constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
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constexpr uint32_t PA_SC_VPORT_ZMAX_0 = 0xB5;
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constexpr uint32_t PA_SC_VPORT_ZMIN_15 = 0xD2;
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constexpr uint32_t PA_SC_VPORT_ZMAX_15 = 0xD3;
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constexpr uint32_t PA_SC_RIGHT_VERT_GRID = 0xE8;
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constexpr uint32_t PA_SC_LEFT_VERT_GRID = 0xE9;
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constexpr uint32_t PA_SC_HORIZ_GRID = 0xEA;
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constexpr uint32_t PA_SC_FOV_WINDOW_LR = 0xEB;
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constexpr uint32_t PA_SC_FOV_WINDOW_TB = 0xEC;
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constexpr uint32_t CB_RMI_GL2_CACHE_CONTROL = 0x104;
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constexpr uint32_t CB_BLEND_RED = 0x105;
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constexpr uint32_t CB_BLEND_GREEN = 0x106;
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constexpr uint32_t CB_BLEND_BLUE = 0x107;
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constexpr uint32_t CB_BLEND_ALPHA = 0x108;
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constexpr uint32_t CB_DCC_CONTROL = 0x109;
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constexpr uint32_t DB_STENCIL_CONTROL = 0x10B;
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constexpr uint32_t DB_STENCIL_CONTROL_STENCILFAIL_SHIFT = 0;
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@@ -295,29 +345,35 @@ constexpr uint32_t DB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK = 0xFF;
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constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_SHIFT = 24;
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constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_MASK = 0xFF;
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constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
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constexpr uint32_t PA_CL_VPORT_XOFFSET = 0x110;
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constexpr uint32_t PA_CL_VPORT_YSCALE = 0x111;
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constexpr uint32_t PA_CL_VPORT_YOFFSET = 0x112;
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constexpr uint32_t PA_CL_VPORT_ZSCALE = 0x113;
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constexpr uint32_t PA_CL_VPORT_ZOFFSET = 0x114;
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constexpr uint32_t PA_CL_UCP_0_X = 0x16F;
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constexpr uint32_t PA_CL_UCP_0_Y = 0x170;
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constexpr uint32_t PA_CL_UCP_0_Z = 0x171;
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constexpr uint32_t PA_CL_UCP_0_W = 0x172;
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constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
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constexpr uint32_t SPI_PS_INPUT_CNTL_31 = 0x1B0;
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constexpr uint32_t SPI_VS_OUT_CONFIG = 0x1B1;
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constexpr uint32_t SPI_PS_INPUT_ENA = 0x1B3;
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constexpr uint32_t SPI_PS_INPUT_ADDR = 0x1B4;
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constexpr uint32_t SPI_INTERP_CONTROL_0 = 0x1B5;
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constexpr uint32_t SPI_PS_IN_CONTROL = 0x1B6;
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constexpr uint32_t SPI_BARYC_CNTL = 0x1B8;
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constexpr uint32_t SPI_TMPRING_SIZE = 0x1BA;
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constexpr uint32_t SPI_SHADER_IDX_FORMAT = 0x1C2;
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constexpr uint32_t SPI_SHADER_POS_FORMAT = 0x1C3;
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constexpr uint32_t SPI_SHADER_Z_FORMAT = 0x1C4;
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constexpr uint32_t SPI_SHADER_COL_FORMAT = 0x1C5;
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constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
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constexpr uint32_t PA_CL_VPORT_XOFFSET = 0x110;
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constexpr uint32_t PA_CL_VPORT_YSCALE = 0x111;
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constexpr uint32_t PA_CL_VPORT_YOFFSET = 0x112;
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constexpr uint32_t PA_CL_VPORT_ZSCALE = 0x113;
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constexpr uint32_t PA_CL_VPORT_ZOFFSET = 0x114;
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constexpr uint32_t PA_CL_VPORT_XSCALE_15 = 0x169;
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constexpr uint32_t PA_CL_VPORT_XOFFSET_15 = 0x16A;
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constexpr uint32_t PA_CL_VPORT_YSCALE_15 = 0x16B;
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constexpr uint32_t PA_CL_VPORT_YOFFSET_15 = 0x16C;
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constexpr uint32_t PA_CL_VPORT_ZSCALE_15 = 0x16D;
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constexpr uint32_t PA_CL_VPORT_ZOFFSET_15 = 0x16E;
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constexpr uint32_t PA_CL_UCP_0_X = 0x16F;
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constexpr uint32_t PA_CL_UCP_0_Y = 0x170;
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constexpr uint32_t PA_CL_UCP_0_Z = 0x171;
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constexpr uint32_t PA_CL_UCP_0_W = 0x172;
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constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
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constexpr uint32_t SPI_PS_INPUT_CNTL_31 = 0x1B0;
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constexpr uint32_t SPI_VS_OUT_CONFIG = 0x1B1;
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constexpr uint32_t SPI_PS_INPUT_ENA = 0x1B3;
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constexpr uint32_t SPI_PS_INPUT_ADDR = 0x1B4;
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constexpr uint32_t SPI_INTERP_CONTROL_0 = 0x1B5;
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constexpr uint32_t SPI_PS_IN_CONTROL = 0x1B6;
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constexpr uint32_t SPI_BARYC_CNTL = 0x1B8;
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constexpr uint32_t SPI_TMPRING_SIZE = 0x1BA;
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constexpr uint32_t SPI_SHADER_IDX_FORMAT = 0x1C2;
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constexpr uint32_t SPI_SHADER_POS_FORMAT = 0x1C3;
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constexpr uint32_t SPI_SHADER_Z_FORMAT = 0x1C4;
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constexpr uint32_t SPI_SHADER_COL_FORMAT = 0x1C5;
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constexpr uint32_t CB_BLEND0_CONTROL = 0x1E0;
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constexpr uint32_t CB_BLEND0_CONTROL_COLOR_SRCBLEND_SHIFT = 0;
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@@ -339,23 +395,27 @@ constexpr uint32_t CB_BLEND0_CONTROL_ENABLE_MASK = 0x1;
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constexpr uint32_t GE_MAX_OUTPUT_PER_SUBGROUP = 0x1FF;
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constexpr uint32_t DB_DEPTH_CONTROL = 0x200;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_SHIFT = 1;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_SHIFT = 2;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_SHIFT = 3;
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constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_SHIFT = 4;
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constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_MASK = 0x7;
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constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_SHIFT = 7;
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constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_SHIFT = 8;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_MASK = 0x7;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_SHIFT = 20;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_MASK = 0x7;
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constexpr uint32_t DB_DEPTH_CONTROL = 0x200;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_SHIFT = 1;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_SHIFT = 2;
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constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_SHIFT = 3;
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constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_SHIFT = 4;
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constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_MASK = 0x7;
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constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_SHIFT = 7;
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constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_SHIFT = 8;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_MASK = 0x7;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_SHIFT = 20;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_MASK = 0x7;
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constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_SHIFT = 30;
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constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK = 0x1;
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constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_SHIFT = 31;
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constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK = 0x1;
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constexpr uint32_t DB_EQAA = 0x201;
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constexpr uint32_t DB_EQAA_MAX_ANCHOR_SAMPLES_SHIFT = 0;
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@@ -539,21 +599,124 @@ constexpr uint32_t PA_SC_BINNER_CNTL_1 = 0x312;
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constexpr uint32_t PA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x313;
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constexpr uint32_t PA_SC_NGG_MODE_CNTL = 0x314;
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constexpr uint32_t CB_COLOR0_BASE = 0x318;
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constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
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constexpr uint32_t CB_COLOR0_INFO = 0x31C;
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constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
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constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
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constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
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constexpr uint32_t CB_COLOR0_FMASK = 0x321;
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constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
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constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_START_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_START_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_MAX_SHIFT = 13;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_MAX_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_MIP_LEVEL_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_MIP_LEVEL_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FORMAT_SHIFT = 2;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FORMAT_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_INFO_NUMBER_TYPE_SHIFT = 8;
|
||||
constexpr uint32_t CB_COLOR0_INFO_NUMBER_TYPE_MASK = 0x7;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMP_SWAP_SHIFT = 11;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMP_SWAP_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FAST_CLEAR_SHIFT = 13;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FAST_CLEAR_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMPRESSION_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMPRESSION_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_CLAMP_SHIFT = 15;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_SHIFT = 16;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_SHIFT = 18;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_SHIFT = 19;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_SHIFT = 27;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_SHIFT = 28;
|
||||
constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_SHIFT = 29;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_SHIFT = 31;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_SHIFT = 5;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_SHIFT = 12;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_MASK = 0x7;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_FRAGMENTS_SHIFT = 15;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_FRAGMENTS_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FORCE_DST_ALPHA_1_SHIFT = 17;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FORCE_DST_ALPHA_1_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_OVERWRITE_COMBINER_DISABLE_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_OVERWRITE_COMBINER_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_SHIFT = 1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_SHIFT = 2;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_SHIFT = 4;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_SHIFT = 5;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_COLOR_TRANSFORM_SHIFT = 7;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_COLOR_TRANSFORM_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_64B_BLOCKS_SHIFT = 9;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_64B_BLOCKS_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_ENABLE_CONSTANT_ENCODE_REG_WRITE_SHIFT = 19;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_128B_BLOCKS_SHIFT = 20;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_128B_BLOCKS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR7_BASE = 0x381;
|
||||
constexpr uint32_t CB_COLOR7_VIEW = 0x384;
|
||||
constexpr uint32_t CB_COLOR7_INFO = 0x385;
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB = 0x386;
|
||||
constexpr uint32_t CB_COLOR7_DCC_CONTROL = 0x387;
|
||||
constexpr uint32_t CB_COLOR7_CMASK = 0x388;
|
||||
constexpr uint32_t CB_COLOR7_FMASK = 0x38A;
|
||||
constexpr uint32_t CB_COLOR7_CLEAR_WORD0 = 0x38C;
|
||||
constexpr uint32_t CB_COLOR7_CLEAR_WORD1 = 0x38D;
|
||||
constexpr uint32_t CB_COLOR7_DCC_BASE = 0x38E;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR7_BASE_EXT = 0x397;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR7_CMASK_BASE_EXT = 0x39F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR7_FMASK_BASE_EXT = 0x3A7;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR7_DCC_BASE_EXT = 0x3AF;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_HEIGHT_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_HEIGHT_MASK = 0x3FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_WIDTH_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_WIDTH_MASK = 0x3FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MAX_MIP_SHIFT = 28;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MAX_MIP_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB2 = 0x3B7;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_MIP0_DEPTH_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_MIP0_DEPTH_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_COLOR_SW_MODE_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_COLOR_SW_MODE_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_RESOURCE_TYPE_SHIFT = 24;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_RESOURCE_TYPE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_SHIFT = 30;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB3 = 0x3BF;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
@@ -572,23 +735,86 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC3_PS = 0x7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_PS = 0x8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_PS = 0x9;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS = 0xA;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS = 0xA;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DEBUG_MODE_SHIFT = 22;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DEBUG_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_CU_GROUP_DISABLE_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_CU_GROUP_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FWD_PROGRESS_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_SHIFT = 29;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS = 0xB;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS = 0xB;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_SHIFT = 8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_VS = 0x48;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_VS = 0x49;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS = 0x4A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPR_COMP_CNT_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_CU_GROUP_ENABLE_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_CU_GROUP_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FWD_PROGRESS_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FP16_OVFL_SHIFT = 31;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS = 0x4B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_OC_LDS_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_OC_LDS_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SO_EN_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SO_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_0 = 0x4C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_15 = 0x5B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_GS = 0x80;
|
||||
@@ -598,9 +824,51 @@ constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_GS = 0x83;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_GS = 0x87;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_GS = 0x88;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_GS = 0x89;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS = 0x8A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS = 0x8B;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS = 0x8A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DEBUG_MODE_SHIFT = 22;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DEBUG_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_CU_GROUP_ENABLE_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_CU_GROUP_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FWD_PROGRESS_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_WGP_MODE_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_WGP_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_GS_VGPR_COMP_CNT_SHIFT = 29;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_GS_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FP16_OVFL_SHIFT = 31;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS = 0x8B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_ES_VGPR_COMP_CNT_SHIFT = 16;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_ES_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_OC_LDS_EN_SHIFT = 18;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_OC_LDS_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_LDS_SIZE_SHIFT = 19;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_LDS_SIZE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_0 = 0x8C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_15 = 0x9B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0 = 0xB2;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_ES = 0xC8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_ES = 0xC9;
|
||||
@@ -670,24 +938,41 @@ constexpr uint32_t SH_NUM = 0x2FF + 1;
|
||||
|
||||
/* User config registers */
|
||||
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE_PRIM_TYPE_SHIFT = 0;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE_PRIM_TYPE_MASK = 0x3F;
|
||||
|
||||
constexpr uint32_t VGT_OBJECT_ID = 0x248;
|
||||
constexpr uint32_t GE_INDX_OFFSET = 0x24A;
|
||||
constexpr uint32_t GE_MULTI_PRIM_IB_RESET_EN = 0x24B;
|
||||
constexpr uint32_t VGT_HS_OFFCHIP_PARAM = 0x24F;
|
||||
constexpr uint32_t VGT_TF_MEMORY_BASE = 0x250;
|
||||
constexpr uint32_t GE_CNTL = 0x25B;
|
||||
constexpr uint32_t GE_USER_VGPR1 = 0x25C;
|
||||
constexpr uint32_t GE_USER_VGPR2 = 0x25D;
|
||||
constexpr uint32_t GE_USER_VGPR3 = 0x25E;
|
||||
constexpr uint32_t GE_STEREO_CNTL = 0x25F;
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR = 0x380;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR_HI = 0x381;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
|
||||
constexpr uint32_t GDS_OA_CNTL = 0x41D;
|
||||
constexpr uint32_t GDS_OA_COUNTER = 0x41E;
|
||||
constexpr uint32_t GDS_OA_ADDRESS = 0x41F;
|
||||
|
||||
constexpr uint32_t GE_CNTL = 0x25B;
|
||||
constexpr uint32_t GE_CNTL_PRIM_GRP_SIZE_SHIFT = 0;
|
||||
constexpr uint32_t GE_CNTL_PRIM_GRP_SIZE_MASK = 0x1FF;
|
||||
constexpr uint32_t GE_CNTL_VERT_GRP_SIZE_SHIFT = 9;
|
||||
constexpr uint32_t GE_CNTL_VERT_GRP_SIZE_MASK = 0x1FF;
|
||||
|
||||
constexpr uint32_t GE_USER_VGPR1 = 0x25C;
|
||||
constexpr uint32_t GE_USER_VGPR2 = 0x25D;
|
||||
constexpr uint32_t GE_USER_VGPR3 = 0x25E;
|
||||
constexpr uint32_t GE_STEREO_CNTL = 0x25F;
|
||||
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR1_SHIFT = 0;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR1_MASK = 0x1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR2_SHIFT = 1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR2_MASK = 0x1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_SHIFT = 2;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR = 0x380;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR_HI = 0x381;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
|
||||
constexpr uint32_t GDS_OA_CNTL = 0x41D;
|
||||
constexpr uint32_t GDS_OA_COUNTER = 0x41E;
|
||||
constexpr uint32_t GDS_OA_ADDRESS = 0x41F;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
|
||||
Reference in New Issue
Block a user