mirror of
https://github.com/InoriRus/Kyty.git
synced 2026-08-28 05:06:40 +00:00
PS5 graphics (#42)
This commit is contained in:
InoriRus
@@ -29,20 +29,26 @@ struct ColorView
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{
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uint32_t base_array_slice_index = 0;
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uint32_t last_array_slice_index = 0;
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uint32_t current_mip_level = 0;
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};
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struct ColorInfo
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{
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bool fmask_compression_enable = false;
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uint32_t fmask_compression_mode = 0;
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bool cmask_fast_clear_enable = false;
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bool dcc_compression_enable = false;
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bool neo_mode = false;
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uint32_t cmask_tile_mode = 0;
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uint32_t cmask_tile_mode_neo = 0;
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uint32_t format = 0;
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uint32_t channel_type = 0;
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uint32_t channel_order = 0;
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bool fmask_compression_enable = false;
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// uint32_t fmask_compression_mode = 0;
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bool fmask_data_compression_disable = false;
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bool fmask_one_frag_mode = false;
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bool cmask_fast_clear_enable = false;
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bool dcc_compression_enable = false;
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bool neo_mode = false;
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bool blend_clamp = false;
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bool blend_bypass = false;
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bool round_mode = false;
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uint32_t cmask_tile_mode = 0;
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uint32_t cmask_tile_mode_neo = 0;
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uint32_t format = 0;
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uint32_t channel_type = 0;
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uint32_t channel_order = 0;
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};
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struct ColorAttrib
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@@ -54,14 +60,33 @@ struct ColorAttrib
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uint32_t num_fragments = 0;
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};
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struct ColorDcc
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struct ColorAttrib2
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{
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uint32_t max_uncompressed_block_size = 0;
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uint32_t max_compressed_block_size = 0;
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uint32_t min_compressed_block_size = 0;
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uint32_t color_transform = 0;
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bool enable_overwrite_combiner = false;
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bool force_independent_blocks = false;
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uint32_t height = 0;
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uint32_t width = 0;
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uint32_t num_mip_levels = 0;
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};
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struct ColorAttrib3
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{
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uint32_t depth = 0;
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uint32_t tile_mode = 0;
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uint32_t dimension = 0;
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bool cmask_pipe_aligned = false;
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bool dcc_pipe_aligned = false;
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};
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struct ColorDccControl
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{
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uint32_t max_uncompressed_block_size = 0;
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uint32_t max_compressed_block_size = 0;
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uint32_t min_compressed_block_size = 0;
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uint32_t color_transform = 0;
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bool dcc_clear_key_enable = false;
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bool overwrite_combiner_disable = false;
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bool independent_64b_blocks = false;
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bool independent_128b_blocks = false;
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bool data_write_on_dcc_clear_to_reg = false;
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};
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struct ColorCmask
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@@ -113,7 +138,9 @@ struct RenderTarget
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ColorView view;
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ColorInfo info;
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ColorAttrib attrib;
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ColorDcc dcc;
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ColorAttrib2 attrib2;
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ColorAttrib3 attrib3;
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ColorDccControl dcc;
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ColorCmask cmask;
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ColorCmaskSlice cmask_slice;
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ColorFmask fmask;
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@@ -124,23 +151,29 @@ struct RenderTarget
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ColorSize size;
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};
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struct DepthRenderTargetZInfo
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struct DepthZInfo
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{
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uint32_t format = 0;
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uint32_t tile_mode_index = 0;
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uint32_t num_samples = 0;
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bool tile_surface_enable = false;
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bool expclear_enabled = false;
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uint32_t zrange_precision = 0;
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uint32_t format = 0;
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uint32_t tile_mode_index = 0;
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uint32_t num_samples = 0;
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uint32_t zrange_precision = 0;
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bool tile_surface_enable = false;
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bool expclear_enabled = false;
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bool embedded_sample_locations = false;
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bool partially_resident = false;
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uint8_t num_mip_levels = 0;
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uint8_t plane_compression = 0;
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};
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struct DepthRenderTargetStencilInfo
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struct DepthStencilInfo
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{
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uint32_t format = 0;
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uint32_t tile_mode_index = 0;
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uint32_t tile_split = 0;
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bool expclear_enabled = false;
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bool tile_stencil_disable = false;
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uint32_t format = 0;
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uint32_t tile_mode_index = 0;
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uint32_t tile_split = 0;
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bool expclear_enabled = false;
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bool tile_stencil_disable = false;
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bool texture_compatible_stencil = false;
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bool partially_resident = false;
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};
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struct DepthRenderTargetDepthInfo
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@@ -154,10 +187,19 @@ struct DepthRenderTargetDepthInfo
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uint32_t num_banks = 0;
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};
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struct DepthRenderTargetDepthView
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struct DepthDepthView
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{
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uint32_t slice_start = 0;
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uint32_t slice_max = 0;
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uint32_t slice_start = 0;
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uint32_t slice_max = 0;
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uint8_t current_mip_level = 0;
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bool depth_write_disable = false;
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bool stencil_write_disable = false;
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};
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struct DepthDepthSizeXY
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{
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uint16_t x_max = 0;
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uint16_t y_max = 0;
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};
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struct DepthRenderTargetHTileSurface
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@@ -173,10 +215,11 @@ struct DepthRenderTargetHTileSurface
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struct DepthRenderTarget
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{
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DepthRenderTargetZInfo z_info;
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DepthRenderTargetStencilInfo stencil_info;
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DepthZInfo z_info;
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DepthStencilInfo stencil_info;
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DepthDepthView depth_view;
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DepthDepthSizeXY size;
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DepthRenderTargetDepthInfo depth_info;
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DepthRenderTargetDepthView depth_view;
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DepthRenderTargetHTileSurface htile_surface;
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uint64_t z_read_base_addr = 0;
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@@ -220,14 +263,16 @@ struct ClipControl
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struct DepthControl
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{
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bool stencil_enable = false;
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bool z_enable = false;
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bool z_write_enable = false;
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bool depth_bounds_enable = false;
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uint8_t zfunc = 0;
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bool backface_enable = false;
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uint8_t stencilfunc = 0;
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uint8_t stencilfunc_bf = 0;
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bool stencil_enable = false;
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bool z_enable = false;
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bool z_write_enable = false;
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bool depth_bounds_enable = false;
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uint8_t zfunc = 0;
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bool backface_enable = false;
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uint8_t stencilfunc = 0;
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uint8_t stencilfunc_bf = 0;
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bool color_writes_on_depth_fail_enable = false;
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bool color_writes_on_depth_pass_disable = false;
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};
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struct StencilControl
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@@ -374,29 +419,66 @@ struct ScreenViewport
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float guard_band_vert_discard = 0.0f;
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};
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struct VsShaderResource1
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{
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t priority = 0;
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uint8_t float_mode = 0;
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bool dx10_clamp = false;
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bool ieee_mode = false;
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uint8_t vgpr_component_count = 0;
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bool cu_group_enable = false;
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bool require_forward_progress = false;
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bool fp16_overflow = false;
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};
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struct VsShaderResource2
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{
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bool scratch_en = false;
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uint8_t user_sgpr = 0;
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bool offchip_lds = false;
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bool streamout_enabled = false;
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uint8_t shared_vgprs = 0;
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};
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struct VsStageRegisters
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{
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uint32_t m_spiShaderPgmLoVs = 0;
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uint32_t m_spiShaderPgmHiVs = 0;
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uint32_t m_spiShaderPgmRsrc1Vs = 0;
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uint32_t m_spiShaderPgmRsrc2Vs = 0;
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uint64_t data_addr = 0;
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VsShaderResource1 rsrc1;
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VsShaderResource2 rsrc2;
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};
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[[nodiscard]] uint64_t GetGpuAddress() const;
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[[nodiscard]] bool GetStreamoutEnabled() const;
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[[nodiscard]] uint32_t GetSgprCount() const;
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[[nodiscard]] uint32_t GetInputComponentsCount() const;
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[[nodiscard]] uint32_t GetUnknown1() const;
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[[nodiscard]] uint32_t GetUnknown2() const;
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struct PsShaderResource1
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{
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t priority = 0;
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uint8_t float_mode = 0;
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bool dx10_clamp = false;
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bool debug_mode = false;
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bool ieee_mode = false;
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bool cu_group_disable = false;
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bool require_forward_progress = false;
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bool fp16_overflow = false;
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};
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struct PsShaderResource2
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{
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bool scratch_en = false;
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uint8_t user_sgpr = 0;
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bool wave_cnt_en = false;
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uint8_t extra_lds_size = 0;
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bool raster_ordered_shading = false;
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uint8_t shared_vgprs = 0;
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};
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struct PsStageRegisters
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{
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uint64_t data_addr = 0;
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t scratch_en = 0;
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uint8_t user_sgpr = 0;
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uint8_t wave_cnt_en = 0;
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uint64_t data_addr = 0;
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PsShaderResource1 rsrc1;
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PsShaderResource2 rsrc2;
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uint64_t chksum = 0;
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};
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struct CsStageRegisters
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@@ -419,6 +501,45 @@ struct CsStageRegisters
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uint8_t lds_size = 0;
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};
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struct EsStageRegisters
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{
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uint64_t data_addr = 0;
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};
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struct GsShaderResource1
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{
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t priority = 0;
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uint8_t float_mode = 0;
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bool dx10_clamp = false;
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bool debug_mode = false;
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bool ieee_mode = false;
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bool cu_group_enable = false;
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bool require_forward_progress = false;
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bool lds_configuration = false;
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uint8_t gs_vgpr_component_count = 0;
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bool fp16_overflow = false;
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};
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struct GsShaderResource2
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{
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bool scratch_en = false;
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uint8_t user_sgpr = 0;
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uint8_t es_vgpr_component_count = 0;
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bool offchip_lds = false;
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uint8_t lds_size = 0;
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uint8_t shared_vgprs = 0;
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};
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struct GsStageRegisters
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{
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uint64_t data_addr = 0;
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GsShaderResource1 rsrc1;
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GsShaderResource2 rsrc2;
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uint64_t chksum = 0;
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};
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struct ShaderRegisters
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{
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uint32_t m_spiVsOutConfig = 0;
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@@ -472,9 +593,12 @@ struct UserSgprInfo
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struct VertexShaderInfo
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{
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VsStageRegisters vs_regs;
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EsStageRegisters es_regs;
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GsStageRegisters gs_regs;
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uint32_t vs_shader_modifier = 0;
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uint32_t vs_embedded_id = 0;
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UserSgprInfo vs_user_sgpr;
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UserSgprInfo gs_user_sgpr;
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bool vs_embedded = false;
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};
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@@ -493,6 +617,19 @@ struct ComputeShaderInfo
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UserSgprInfo cs_user_sgpr;
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};
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struct GeControl
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{
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uint16_t primitive_group_size = 0;
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uint16_t vertex_group_size = 0;
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};
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struct GeUserVgprEn
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{
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bool vgpr1 = false;
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bool vgpr2 = false;
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bool vgpr3 = false;
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};
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class Context
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{
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public:
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@@ -509,7 +646,9 @@ public:
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void SetColorView(uint32_t slot, const ColorView& view) { m_render_targets[slot].view = view; }
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void SetColorInfo(uint32_t slot, const ColorInfo& info) { m_render_targets[slot].info = info; }
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void SetColorAttrib(uint32_t slot, const ColorAttrib& attrib) { m_render_targets[slot].attrib = attrib; }
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void SetColorDcc(uint32_t slot, const ColorDcc& dcc) { m_render_targets[slot].dcc = dcc; }
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void SetColorAttrib2(uint32_t slot, const ColorAttrib2& attrib2) { m_render_targets[slot].attrib2 = attrib2; }
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void SetColorAttrib3(uint32_t slot, const ColorAttrib3& attrib3) { m_render_targets[slot].attrib3 = attrib3; }
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void SetColorDccControl(uint32_t slot, const ColorDccControl& dcc) { m_render_targets[slot].dcc = dcc; }
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void SetColorCmask(uint32_t slot, const ColorCmask& cmask) { m_render_targets[slot].cmask = cmask; }
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void SetColorCmaskSlice(uint32_t slot, const ColorCmaskSlice& cmask_slice) { m_render_targets[slot].cmask_slice = cmask_slice; }
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void SetColorFmask(uint32_t slot, const ColorFmask& fmask) { m_render_targets[slot].fmask = fmask; }
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@@ -531,16 +670,27 @@ public:
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void SetDepthRenderTarget(const DepthRenderTarget& target) { m_depth_render_target = target; }
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[[nodiscard]] const DepthRenderTarget& GetDepthRenderTarget() const { return m_depth_render_target; }
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void SetDepthRenderTargetZInfo(const DepthRenderTargetZInfo& info) { m_depth_render_target.z_info = info; }
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[[nodiscard]] const DepthRenderTargetZInfo& GetDepthRenderTargetZInfo() const { return m_depth_render_target.z_info; }
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void SetDepthRenderTargetStencilInfo(const DepthRenderTargetStencilInfo& info) { m_depth_render_target.stencil_info = info; }
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[[nodiscard]] const DepthRenderTargetStencilInfo& GetDepthRenderTargetStencilInfo() const { return m_depth_render_target.stencil_info; }
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void SetDepthZInfo(const DepthZInfo& info) { m_depth_render_target.z_info = info; }
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[[nodiscard]] const DepthZInfo& GetDepthZInfo() const { return m_depth_render_target.z_info; }
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void SetDepthStencilInfo(const DepthStencilInfo& info) { m_depth_render_target.stencil_info = info; }
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[[nodiscard]] const DepthStencilInfo& GetDepthStencilInfo() const { return m_depth_render_target.stencil_info; }
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void SetDepthZReadBase(uint64_t addr) { m_depth_render_target.z_read_base_addr = addr; }
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void SetDepthStencilReadBase(uint64_t addr) { m_depth_render_target.stencil_read_base_addr = addr; }
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void SetDepthZWriteBase(uint64_t addr) { m_depth_render_target.z_write_base_addr = addr; }
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void SetDepthStencilWriteBase(uint64_t addr) { m_depth_render_target.stencil_write_base_addr = addr; }
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void SetDepthHTileDataBase(uint64_t addr) { m_depth_render_target.htile_data_base_addr = addr; }
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void SetDepthDepthView(const DepthDepthView& view) { m_depth_render_target.depth_view = view; }
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[[nodiscard]] const DepthDepthView& GetDepthDepthView() const { return m_depth_render_target.depth_view; }
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void SetDepthDepthSizeXY(const DepthDepthSizeXY& size) { m_depth_render_target.size = size; }
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[[nodiscard]] const DepthDepthSizeXY& GetDepthDepthSizeXY() const { return m_depth_render_target.size; }
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void SetViewportZ(uint32_t viewport_id, float zmin, float zmax)
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{
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m_screen_viewport.viewports[viewport_id].zmin = zmin;
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m_screen_viewport.viewports[viewport_id].zmax = zmax;
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}
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void SetViewportZMin(uint32_t viewport_id, float zmin) { m_screen_viewport.viewports[viewport_id].zmin = zmin; }
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void SetViewportZMax(uint32_t viewport_id, float zmax) { m_screen_viewport.viewports[viewport_id].zmax = zmax; }
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void SetViewportScaleOffset(uint32_t viewport_id, float xscale, float xoffset, float yscale, float yoffset, float zscale, float zoffset)
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{
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m_screen_viewport.viewports[viewport_id].xscale = xscale;
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@@ -550,6 +700,31 @@ public:
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m_screen_viewport.viewports[viewport_id].zscale = zscale;
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m_screen_viewport.viewports[viewport_id].zoffset = zoffset;
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}
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void SetViewportXScale(uint32_t viewport_id, float xscale) { m_screen_viewport.viewports[viewport_id].xscale = xscale; }
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void SetViewportXOffset(uint32_t viewport_id, float xoffset) { m_screen_viewport.viewports[viewport_id].xoffset = xoffset; }
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void SetViewportYScale(uint32_t viewport_id, float yscale) { m_screen_viewport.viewports[viewport_id].yscale = yscale; }
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void SetViewportYOffset(uint32_t viewport_id, float yoffset) { m_screen_viewport.viewports[viewport_id].yoffset = yoffset; }
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void SetViewportZScale(uint32_t viewport_id, float zscale) { m_screen_viewport.viewports[viewport_id].zscale = zscale; }
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void SetViewportZOffset(uint32_t viewport_id, float zoffset) { m_screen_viewport.viewports[viewport_id].zoffset = zoffset; }
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void SetViewportScissor(uint32_t viewport_id, int left, int top, int right, int bottom, bool window_offset_enable)
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{
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m_screen_viewport.viewports[viewport_id].viewport_scissor_left = left;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_top = top;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_right = right;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_bottom = bottom;
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m_screen_viewport.viewports[viewport_id].viewport_scissor_window_offset_enable = window_offset_enable;
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}
|
||||
void SetViewportScissorTL(uint32_t viewport_id, int left, int top, bool window_offset_enable)
|
||||
{
|
||||
m_screen_viewport.viewports[viewport_id].viewport_scissor_left = left;
|
||||
m_screen_viewport.viewports[viewport_id].viewport_scissor_top = top;
|
||||
m_screen_viewport.viewports[viewport_id].viewport_scissor_window_offset_enable = window_offset_enable;
|
||||
}
|
||||
void SetViewportScissorBR(uint32_t viewport_id, int right, int bottom)
|
||||
{
|
||||
m_screen_viewport.viewports[viewport_id].viewport_scissor_right = right;
|
||||
m_screen_viewport.viewports[viewport_id].viewport_scissor_bottom = bottom;
|
||||
}
|
||||
void SetViewportTransformControl(uint32_t control) { m_screen_viewport.transform_control = control; }
|
||||
void SetScreenScissor(int left, int top, int right, int bottom)
|
||||
{
|
||||
@@ -688,8 +863,16 @@ public:
|
||||
void SetPrimitiveType(uint32_t prim_type) { m_prim_type = prim_type; }
|
||||
[[nodiscard]] uint32_t GetPrimType() const { return m_prim_type; }
|
||||
|
||||
[[nodiscard]] const GeControl& GetGeControl() const { return m_ge_cntl; }
|
||||
void SetGeControl(const GeControl& control) { m_ge_cntl = control; }
|
||||
[[nodiscard]] const GeUserVgprEn& GetGeUserVgprEn() const { return m_ge_user_vgpr_en; }
|
||||
void SetGeUserVgprEn(const GeUserVgprEn& en) { m_ge_user_vgpr_en = en; }
|
||||
|
||||
private:
|
||||
uint32_t m_prim_type = 0;
|
||||
|
||||
GeControl m_ge_cntl;
|
||||
GeUserVgprEn m_ge_user_vgpr_en;
|
||||
};
|
||||
|
||||
class Shader
|
||||
@@ -702,49 +885,75 @@ public:
|
||||
|
||||
void Reset() { *this = Shader(); }
|
||||
|
||||
void SetVsShader(const VsStageRegisters& vs_regs, uint32_t shader_modifier)
|
||||
void SetVsShaderModifier(uint32_t shader_modifier) { m_vs.vs_shader_modifier = shader_modifier; }
|
||||
void SetVsShaderBase(uint64_t addr)
|
||||
{
|
||||
m_vs.vs_regs = vs_regs;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = false;
|
||||
m_vs.vs_regs.data_addr = addr;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetVsShaderResource1(const VsShaderResource1& rsrc1)
|
||||
{
|
||||
m_vs.vs_regs.rsrc1 = rsrc1;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetVsShaderResource2(const VsShaderResource2& rsrc2)
|
||||
{
|
||||
m_vs.vs_regs.rsrc2 = rsrc2;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
|
||||
void UpdateVsShader(const VsStageRegisters& vs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
m_vs.vs_regs.m_spiShaderPgmLoVs = vs_regs.m_spiShaderPgmLoVs;
|
||||
m_vs.vs_regs.m_spiShaderPgmHiVs = vs_regs.m_spiShaderPgmHiVs;
|
||||
m_vs.vs_regs.m_spiShaderPgmRsrc1Vs = vs_regs.m_spiShaderPgmRsrc1Vs;
|
||||
m_vs.vs_regs.m_spiShaderPgmRsrc2Vs = vs_regs.m_spiShaderPgmRsrc2Vs;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetVsEmbedded(uint32_t id, uint32_t shader_modifier)
|
||||
{
|
||||
m_vs.vs_embedded_id = id;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = true;
|
||||
}
|
||||
|
||||
void SetPsShader(const PsStageRegisters& ps_regs)
|
||||
void SetEsShaderBase(uint64_t addr)
|
||||
{
|
||||
m_ps.ps_regs = ps_regs;
|
||||
m_ps.ps_embedded = false;
|
||||
m_vs.es_regs.data_addr = addr;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void UpdatePsShader(const PsStageRegisters& ps_regs)
|
||||
void SetGsShaderResource1(const GsShaderResource1& rsrc1)
|
||||
{
|
||||
m_ps.ps_regs.data_addr = ps_regs.data_addr;
|
||||
m_ps.ps_regs.vgprs = ps_regs.vgprs;
|
||||
m_ps.ps_regs.sgprs = ps_regs.sgprs;
|
||||
m_ps.ps_regs.scratch_en = ps_regs.scratch_en;
|
||||
m_ps.ps_regs.user_sgpr = ps_regs.user_sgpr;
|
||||
m_ps.ps_regs.wave_cnt_en = ps_regs.wave_cnt_en;
|
||||
m_ps.ps_embedded = false;
|
||||
m_vs.gs_regs.rsrc1 = rsrc1;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetGsShaderResource2(const GsShaderResource2& rsrc2)
|
||||
{
|
||||
m_vs.gs_regs.rsrc2 = rsrc2;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetGsShaderChksum(uint32_t value)
|
||||
{
|
||||
m_vs.gs_regs.chksum <<= 32u;
|
||||
m_vs.gs_regs.chksum |= value;
|
||||
}
|
||||
|
||||
void SetPsShaderBase(uint64_t addr)
|
||||
{
|
||||
m_ps.ps_regs.data_addr = addr;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void SetPsShaderResource1(const PsShaderResource1& rsrc1)
|
||||
{
|
||||
m_ps.ps_regs.rsrc1 = rsrc1;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void SetPsShaderResource2(const PsShaderResource2& rsrc2)
|
||||
{
|
||||
m_ps.ps_regs.rsrc2 = rsrc2;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void SetPsEmbedded(uint32_t id)
|
||||
{
|
||||
m_ps.ps_embedded_id = id;
|
||||
m_ps.ps_embedded = true;
|
||||
}
|
||||
void SetPsShaderChksum(uint32_t value)
|
||||
{
|
||||
m_ps.ps_regs.chksum <<= 32u;
|
||||
m_ps.ps_regs.chksum |= value;
|
||||
}
|
||||
|
||||
void SetCsShader(const CsStageRegisters& cs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
@@ -770,6 +979,12 @@ public:
|
||||
m_cs.cs_user_sgpr.type[id] = type;
|
||||
m_cs.cs_user_sgpr.count = ((id + 1) > m_cs.cs_user_sgpr.count ? (id + 1) : m_cs.cs_user_sgpr.count);
|
||||
}
|
||||
void SetGsUserSgpr(uint32_t id, uint32_t value, UserSgprType type)
|
||||
{
|
||||
m_vs.gs_user_sgpr.value[id] = value;
|
||||
m_vs.gs_user_sgpr.type[id] = type;
|
||||
m_vs.gs_user_sgpr.count = ((id + 1) > m_vs.gs_user_sgpr.count ? (id + 1) : m_vs.gs_user_sgpr.count);
|
||||
}
|
||||
|
||||
[[nodiscard]] const PixelShaderInfo& GetPs() const { return m_ps; }
|
||||
[[nodiscard]] const VertexShaderInfo& GetVs() const { return m_vs; }
|
||||
@@ -781,36 +996,6 @@ private:
|
||||
ComputeShaderInfo m_cs;
|
||||
};
|
||||
|
||||
inline uint64_t VsStageRegisters::GetGpuAddress() const
|
||||
{
|
||||
return (static_cast<uint64_t>(m_spiShaderPgmLoVs) << 8u) | (static_cast<uint64_t>(m_spiShaderPgmHiVs) << 40u);
|
||||
}
|
||||
|
||||
inline bool VsStageRegisters::GetStreamoutEnabled() const
|
||||
{
|
||||
return (m_spiShaderPgmRsrc2Vs & 0x00001000u) != 0u;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetSgprCount() const
|
||||
{
|
||||
return (m_spiShaderPgmRsrc1Vs >> 6u) & 0xfu;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetInputComponentsCount() const
|
||||
{
|
||||
return (m_spiShaderPgmRsrc1Vs >> 24u) & 0x3u;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetUnknown1() const
|
||||
{
|
||||
return m_spiShaderPgmRsrc1Vs & 0xfcfffc3fu;
|
||||
}
|
||||
|
||||
inline uint32_t VsStageRegisters::GetUnknown2() const
|
||||
{
|
||||
return m_spiShaderPgmRsrc2Vs & 0xFFFFEFFFu;
|
||||
}
|
||||
|
||||
} // namespace Kyty::Libs::Graphics::HW
|
||||
|
||||
#endif // KYTY_EMU_ENABLED
|
||||
|
||||
@@ -18,14 +18,16 @@ public:
|
||||
static constexpr int PARAM_HEIGHT = 2;
|
||||
static constexpr int PARAM_HTILE = 3;
|
||||
static constexpr int PARAM_NEO = 4;
|
||||
static constexpr int PARAM_USAGE = 5;
|
||||
|
||||
DepthStencilBufferObject(uint64_t vk_format, uint32_t width, uint32_t height, bool htile, bool neo)
|
||||
DepthStencilBufferObject(uint64_t vk_format, uint32_t width, uint32_t height, bool htile, bool neo, bool sampled)
|
||||
{
|
||||
params[PARAM_FORMAT] = vk_format;
|
||||
params[PARAM_WIDTH] = width;
|
||||
params[PARAM_HEIGHT] = height;
|
||||
params[PARAM_HTILE] = htile ? 1 : 0;
|
||||
params[PARAM_NEO] = neo ? 1 : 0;
|
||||
params[PARAM_USAGE] = sampled ? 1 : 0;
|
||||
check_hash = false;
|
||||
type = Graphics::GpuMemoryObjectType::DepthStencilBuffer;
|
||||
}
|
||||
|
||||
@@ -120,19 +120,35 @@ constexpr uint32_t DB_RENDER_CONTROL_COPY_SAMPLE_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t DB_COUNT_CONTROL = 0x1;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_VIEW = 0x2;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_MASK = 0x7FF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_SHIFT = 13;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_MASK = 0x7FF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW = 0x2;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_MASK = 0x7FF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_HI_SHIFT = 11;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_HI_MASK = 0x3;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_SHIFT = 13;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_MASK = 0x7FF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_Z_READ_ONLY_SHIFT = 24;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_Z_READ_ONLY_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_STENCIL_READ_ONLY_SHIFT = 25;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_STENCIL_READ_ONLY_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_MIPID_SHIFT = 26;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_MIPID_MASK = 0xF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_HI_SHIFT = 30;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_HI_MASK = 0x3;
|
||||
|
||||
constexpr uint32_t DB_RENDER_OVERRIDE = 0x3;
|
||||
constexpr uint32_t DB_RENDER_OVERRIDE2 = 0x4;
|
||||
constexpr uint32_t DB_HTILE_DATA_BASE = 0x5;
|
||||
constexpr uint32_t PS_SHADER_SAMPLE_EXCLUSION_MASK = 0x6;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MIN = 0x8;
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MAX = 0x9;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_X_MAX_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_X_MAX_MASK = 0x3FFF;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_Y_MAX_SHIFT = 16;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY_Y_MAX_MASK = 0x3FFF;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MIN = 0x8;
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MAX = 0x9;
|
||||
|
||||
constexpr uint32_t DB_STENCIL_CLEAR = 0xA;
|
||||
constexpr uint32_t DB_STENCIL_CLEAR_CLEAR_SHIFT = 0;
|
||||
@@ -172,23 +188,41 @@ constexpr uint32_t DB_DEPTH_INFO_MACRO_TILE_ASPECT_MASK = 0x3;
|
||||
constexpr uint32_t DB_DEPTH_INFO_NUM_BANKS_SHIFT = 19;
|
||||
constexpr uint32_t DB_DEPTH_INFO_NUM_BANKS_MASK = 0x3;
|
||||
|
||||
constexpr uint32_t DB_Z_INFO = 0x10;
|
||||
constexpr uint32_t DB_Z_INFO_FORMAT_SHIFT = 0;
|
||||
constexpr uint32_t DB_Z_INFO_FORMAT_MASK = 0x3;
|
||||
constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_SHIFT = 2;
|
||||
constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_MASK = 0x3;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_SHIFT = 20;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_MASK = 0x7;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_SHIFT = 29;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_SHIFT = 31;
|
||||
constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO = 0x10;
|
||||
constexpr uint32_t DB_Z_INFO_FORMAT_SHIFT = 0;
|
||||
constexpr uint32_t DB_Z_INFO_FORMAT_MASK = 0x3;
|
||||
constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_SHIFT = 2;
|
||||
constexpr uint32_t DB_Z_INFO_NUM_SAMPLES_MASK = 0x3;
|
||||
constexpr uint32_t DB_Z_INFO_ITERATE_FLUSH_SHIFT = 11;
|
||||
constexpr uint32_t DB_Z_INFO_ITERATE_FLUSH_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_PARTIALLY_RESIDENT_SHIFT = 12;
|
||||
constexpr uint32_t DB_Z_INFO_PARTIALLY_RESIDENT_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_MAXMIP_SHIFT = 16;
|
||||
constexpr uint32_t DB_Z_INFO_MAXMIP_MASK = 0xF;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_SHIFT = 20;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_MODE_INDEX_MASK = 0x7;
|
||||
constexpr uint32_t DB_Z_INFO_DECOMPRESS_ON_N_ZPLANES_SHIFT = 23;
|
||||
constexpr uint32_t DB_Z_INFO_DECOMPRESS_ON_N_ZPLANES_MASK = 0xF;
|
||||
constexpr uint32_t DB_Z_INFO_ALLOW_EXPCLEAR_SHIFT = 27;
|
||||
constexpr uint32_t DB_Z_INFO_ALLOW_EXPCLEAR_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_SHIFT = 29;
|
||||
constexpr uint32_t DB_Z_INFO_TILE_SURFACE_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_SHIFT = 31;
|
||||
constexpr uint32_t DB_Z_INFO_ZRANGE_PRECISION_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t DB_STENCIL_INFO = 0x11;
|
||||
constexpr uint32_t DB_STENCIL_INFO_FORMAT_SHIFT = 0;
|
||||
constexpr uint32_t DB_STENCIL_INFO_FORMAT_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ITERATE_FLUSH_SHIFT = 11;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ITERATE_FLUSH_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_PARTIALLY_RESIDENT_SHIFT = 12;
|
||||
constexpr uint32_t DB_STENCIL_INFO_PARTIALLY_RESIDENT_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_RESERVED_FIELD_1_SHIFT = 13;
|
||||
constexpr uint32_t DB_STENCIL_INFO_RESERVED_FIELD_1_MASK = 0x7;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_SHIFT = 20;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_MASK = 0x7;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ALLOW_EXPCLEAR_SHIFT = 27;
|
||||
constexpr uint32_t DB_STENCIL_INFO_ALLOW_EXPCLEAR_MASK = 0x1;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_SHIFT = 29;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_MASK = 0x1;
|
||||
|
||||
@@ -245,21 +279,37 @@ constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_X_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_MASK = 0x7FFF;
|
||||
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL = 0x94;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR = 0x95;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMAX_0 = 0xB5;
|
||||
constexpr uint32_t PA_SC_RIGHT_VERT_GRID = 0xE8;
|
||||
constexpr uint32_t PA_SC_LEFT_VERT_GRID = 0xE9;
|
||||
constexpr uint32_t PA_SC_HORIZ_GRID = 0xEA;
|
||||
constexpr uint32_t PA_SC_FOV_WINDOW_LR = 0xEB;
|
||||
constexpr uint32_t PA_SC_FOV_WINDOW_TB = 0xEC;
|
||||
constexpr uint32_t CB_RMI_GL2_CACHE_CONTROL = 0x104;
|
||||
constexpr uint32_t CB_BLEND_RED = 0x105;
|
||||
constexpr uint32_t CB_BLEND_GREEN = 0x106;
|
||||
constexpr uint32_t CB_BLEND_BLUE = 0x107;
|
||||
constexpr uint32_t CB_BLEND_ALPHA = 0x108;
|
||||
constexpr uint32_t CB_DCC_CONTROL = 0x109;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL = 0x94;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_X_SHIFT = 0;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_X_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_TL_Y_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_WINDOW_OFFSET_DISABLE_SHIFT = 31;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL_WINDOW_OFFSET_DISABLE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR = 0x95;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_X_SHIFT = 0;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_X_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR_BR_Y_MASK = 0x7FFF;
|
||||
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_15_TL = 0xB2;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_15_BR = 0xB3;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMAX_0 = 0xB5;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMIN_15 = 0xD2;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMAX_15 = 0xD3;
|
||||
constexpr uint32_t PA_SC_RIGHT_VERT_GRID = 0xE8;
|
||||
constexpr uint32_t PA_SC_LEFT_VERT_GRID = 0xE9;
|
||||
constexpr uint32_t PA_SC_HORIZ_GRID = 0xEA;
|
||||
constexpr uint32_t PA_SC_FOV_WINDOW_LR = 0xEB;
|
||||
constexpr uint32_t PA_SC_FOV_WINDOW_TB = 0xEC;
|
||||
constexpr uint32_t CB_RMI_GL2_CACHE_CONTROL = 0x104;
|
||||
constexpr uint32_t CB_BLEND_RED = 0x105;
|
||||
constexpr uint32_t CB_BLEND_GREEN = 0x106;
|
||||
constexpr uint32_t CB_BLEND_BLUE = 0x107;
|
||||
constexpr uint32_t CB_BLEND_ALPHA = 0x108;
|
||||
constexpr uint32_t CB_DCC_CONTROL = 0x109;
|
||||
|
||||
constexpr uint32_t DB_STENCIL_CONTROL = 0x10B;
|
||||
constexpr uint32_t DB_STENCIL_CONTROL_STENCILFAIL_SHIFT = 0;
|
||||
@@ -295,29 +345,35 @@ constexpr uint32_t DB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK = 0xFF;
|
||||
constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_SHIFT = 24;
|
||||
constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_MASK = 0xFF;
|
||||
|
||||
constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
|
||||
constexpr uint32_t PA_CL_VPORT_XOFFSET = 0x110;
|
||||
constexpr uint32_t PA_CL_VPORT_YSCALE = 0x111;
|
||||
constexpr uint32_t PA_CL_VPORT_YOFFSET = 0x112;
|
||||
constexpr uint32_t PA_CL_VPORT_ZSCALE = 0x113;
|
||||
constexpr uint32_t PA_CL_VPORT_ZOFFSET = 0x114;
|
||||
constexpr uint32_t PA_CL_UCP_0_X = 0x16F;
|
||||
constexpr uint32_t PA_CL_UCP_0_Y = 0x170;
|
||||
constexpr uint32_t PA_CL_UCP_0_Z = 0x171;
|
||||
constexpr uint32_t PA_CL_UCP_0_W = 0x172;
|
||||
constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
|
||||
constexpr uint32_t SPI_PS_INPUT_CNTL_31 = 0x1B0;
|
||||
constexpr uint32_t SPI_VS_OUT_CONFIG = 0x1B1;
|
||||
constexpr uint32_t SPI_PS_INPUT_ENA = 0x1B3;
|
||||
constexpr uint32_t SPI_PS_INPUT_ADDR = 0x1B4;
|
||||
constexpr uint32_t SPI_INTERP_CONTROL_0 = 0x1B5;
|
||||
constexpr uint32_t SPI_PS_IN_CONTROL = 0x1B6;
|
||||
constexpr uint32_t SPI_BARYC_CNTL = 0x1B8;
|
||||
constexpr uint32_t SPI_TMPRING_SIZE = 0x1BA;
|
||||
constexpr uint32_t SPI_SHADER_IDX_FORMAT = 0x1C2;
|
||||
constexpr uint32_t SPI_SHADER_POS_FORMAT = 0x1C3;
|
||||
constexpr uint32_t SPI_SHADER_Z_FORMAT = 0x1C4;
|
||||
constexpr uint32_t SPI_SHADER_COL_FORMAT = 0x1C5;
|
||||
constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
|
||||
constexpr uint32_t PA_CL_VPORT_XOFFSET = 0x110;
|
||||
constexpr uint32_t PA_CL_VPORT_YSCALE = 0x111;
|
||||
constexpr uint32_t PA_CL_VPORT_YOFFSET = 0x112;
|
||||
constexpr uint32_t PA_CL_VPORT_ZSCALE = 0x113;
|
||||
constexpr uint32_t PA_CL_VPORT_ZOFFSET = 0x114;
|
||||
constexpr uint32_t PA_CL_VPORT_XSCALE_15 = 0x169;
|
||||
constexpr uint32_t PA_CL_VPORT_XOFFSET_15 = 0x16A;
|
||||
constexpr uint32_t PA_CL_VPORT_YSCALE_15 = 0x16B;
|
||||
constexpr uint32_t PA_CL_VPORT_YOFFSET_15 = 0x16C;
|
||||
constexpr uint32_t PA_CL_VPORT_ZSCALE_15 = 0x16D;
|
||||
constexpr uint32_t PA_CL_VPORT_ZOFFSET_15 = 0x16E;
|
||||
constexpr uint32_t PA_CL_UCP_0_X = 0x16F;
|
||||
constexpr uint32_t PA_CL_UCP_0_Y = 0x170;
|
||||
constexpr uint32_t PA_CL_UCP_0_Z = 0x171;
|
||||
constexpr uint32_t PA_CL_UCP_0_W = 0x172;
|
||||
constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
|
||||
constexpr uint32_t SPI_PS_INPUT_CNTL_31 = 0x1B0;
|
||||
constexpr uint32_t SPI_VS_OUT_CONFIG = 0x1B1;
|
||||
constexpr uint32_t SPI_PS_INPUT_ENA = 0x1B3;
|
||||
constexpr uint32_t SPI_PS_INPUT_ADDR = 0x1B4;
|
||||
constexpr uint32_t SPI_INTERP_CONTROL_0 = 0x1B5;
|
||||
constexpr uint32_t SPI_PS_IN_CONTROL = 0x1B6;
|
||||
constexpr uint32_t SPI_BARYC_CNTL = 0x1B8;
|
||||
constexpr uint32_t SPI_TMPRING_SIZE = 0x1BA;
|
||||
constexpr uint32_t SPI_SHADER_IDX_FORMAT = 0x1C2;
|
||||
constexpr uint32_t SPI_SHADER_POS_FORMAT = 0x1C3;
|
||||
constexpr uint32_t SPI_SHADER_Z_FORMAT = 0x1C4;
|
||||
constexpr uint32_t SPI_SHADER_COL_FORMAT = 0x1C5;
|
||||
|
||||
constexpr uint32_t CB_BLEND0_CONTROL = 0x1E0;
|
||||
constexpr uint32_t CB_BLEND0_CONTROL_COLOR_SRCBLEND_SHIFT = 0;
|
||||
@@ -339,23 +395,27 @@ constexpr uint32_t CB_BLEND0_CONTROL_ENABLE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t GE_MAX_OUTPUT_PER_SUBGROUP = 0x1FF;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_CONTROL = 0x200;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_SHIFT = 1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_SHIFT = 2;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_SHIFT = 3;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_SHIFT = 4;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_SHIFT = 7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_SHIFT = 8;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_SHIFT = 20;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL = 0x200;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_SHIFT = 1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_SHIFT = 2;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_Z_WRITE_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_SHIFT = 3;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DEPTH_BOUNDS_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_SHIFT = 4;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ZFUNC_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_SHIFT = 7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_BACKFACE_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_SHIFT = 8;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_SHIFT = 20;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCILFUNC_BF_MASK = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_SHIFT = 30;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_ENABLE_COLOR_WRITES_ON_DEPTH_FAIL_MASK = 0x1;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_SHIFT = 31;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_DISABLE_COLOR_WRITES_ON_DEPTH_PASS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t DB_EQAA = 0x201;
|
||||
constexpr uint32_t DB_EQAA_MAX_ANCHOR_SAMPLES_SHIFT = 0;
|
||||
@@ -539,21 +599,124 @@ constexpr uint32_t PA_SC_BINNER_CNTL_1 = 0x312;
|
||||
constexpr uint32_t PA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x313;
|
||||
constexpr uint32_t PA_SC_NGG_MODE_CNTL = 0x314;
|
||||
constexpr uint32_t CB_COLOR0_BASE = 0x318;
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_START_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_START_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_MAX_SHIFT = 13;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_SLICE_MAX_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_MIP_LEVEL_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_VIEW_MIP_LEVEL_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FORMAT_SHIFT = 2;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FORMAT_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_INFO_NUMBER_TYPE_SHIFT = 8;
|
||||
constexpr uint32_t CB_COLOR0_INFO_NUMBER_TYPE_MASK = 0x7;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMP_SWAP_SHIFT = 11;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMP_SWAP_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FAST_CLEAR_SHIFT = 13;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FAST_CLEAR_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMPRESSION_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_INFO_COMPRESSION_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_CLAMP_SHIFT = 15;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_SHIFT = 16;
|
||||
constexpr uint32_t CB_COLOR0_INFO_BLEND_BYPASS_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_SHIFT = 18;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ROUND_MODE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_SHIFT = 19;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_IS_LINEAR_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESSION_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_SHIFT = 27;
|
||||
constexpr uint32_t CB_COLOR0_INFO_FMASK_COMPRESS_1FRAG_ONLY_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_SHIFT = 28;
|
||||
constexpr uint32_t CB_COLOR0_INFO_DCC_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_SHIFT = 29;
|
||||
constexpr uint32_t CB_COLOR0_INFO_CMASK_ADDR_TYPE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_SHIFT = 31;
|
||||
constexpr uint32_t CB_COLOR0_INFO_ALT_TILE_MODE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_TILE_MODE_INDEX_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_SHIFT = 5;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FMASK_TILE_MODE_INDEX_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_SHIFT = 12;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_SAMPLES_MASK = 0x7;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_FRAGMENTS_SHIFT = 15;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_NUM_FRAGMENTS_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FORCE_DST_ALPHA_1_SHIFT = 17;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB_FORCE_DST_ALPHA_1_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_OVERWRITE_COMBINER_DISABLE_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_OVERWRITE_COMBINER_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_SHIFT = 1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_KEY_CLEAR_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_SHIFT = 2;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_UNCOMPRESSED_BLOCK_SIZE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_SHIFT = 4;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MIN_COMPRESSED_BLOCK_SIZE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_SHIFT = 5;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_MAX_COMPRESSED_BLOCK_SIZE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_COLOR_TRANSFORM_SHIFT = 7;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_COLOR_TRANSFORM_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_64B_BLOCKS_SHIFT = 9;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_64B_BLOCKS_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_ENABLE_CONSTANT_ENCODE_REG_WRITE_SHIFT = 19;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_ENABLE_CONSTANT_ENCODE_REG_WRITE_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_128B_BLOCKS_SHIFT = 20;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL_INDEPENDENT_128B_BLOCKS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR7_BASE = 0x381;
|
||||
constexpr uint32_t CB_COLOR7_VIEW = 0x384;
|
||||
constexpr uint32_t CB_COLOR7_INFO = 0x385;
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB = 0x386;
|
||||
constexpr uint32_t CB_COLOR7_DCC_CONTROL = 0x387;
|
||||
constexpr uint32_t CB_COLOR7_CMASK = 0x388;
|
||||
constexpr uint32_t CB_COLOR7_FMASK = 0x38A;
|
||||
constexpr uint32_t CB_COLOR7_CLEAR_WORD0 = 0x38C;
|
||||
constexpr uint32_t CB_COLOR7_CLEAR_WORD1 = 0x38D;
|
||||
constexpr uint32_t CB_COLOR7_DCC_BASE = 0x38E;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR7_BASE_EXT = 0x397;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR7_CMASK_BASE_EXT = 0x39F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR7_FMASK_BASE_EXT = 0x3A7;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR7_DCC_BASE_EXT = 0x3AF;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_HEIGHT_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_HEIGHT_MASK = 0x3FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_WIDTH_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MIP0_WIDTH_MASK = 0x3FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MAX_MIP_SHIFT = 28;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2_MAX_MIP_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB2 = 0x3B7;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_MIP0_DEPTH_SHIFT = 0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_MIP0_DEPTH_MASK = 0x1FFF;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_COLOR_SW_MODE_SHIFT = 14;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_COLOR_SW_MODE_MASK = 0x1F;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_RESOURCE_TYPE_SHIFT = 24;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_RESOURCE_TYPE_MASK = 0x3;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_SHIFT = 26;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_CMASK_PIPE_ALIGNED_MASK = 0x1;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_SHIFT = 30;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3_DCC_PIPE_ALIGNED_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t CB_COLOR7_ATTRIB3 = 0x3BF;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
@@ -572,23 +735,86 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC3_PS = 0x7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_PS = 0x8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_PS = 0x9;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS = 0xA;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS = 0xA;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DEBUG_MODE_SHIFT = 22;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_DEBUG_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_CU_GROUP_DISABLE_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_CU_GROUP_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FWD_PROGRESS_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_SHIFT = 29;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS = 0xB;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS = 0xB;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_SHIFT = 8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_EXTRA_LDS_SIZE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_LOAD_INTRAWAVE_COLLISION_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_VS = 0x48;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_VS = 0x49;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS = 0x4A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPR_COMP_CNT_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_CU_GROUP_ENABLE_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_CU_GROUP_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FWD_PROGRESS_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FP16_OVFL_SHIFT = 31;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_VS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS = 0x4B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_OC_LDS_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_OC_LDS_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SO_EN_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SO_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_VS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_0 = 0x4C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_15 = 0x5B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_GS = 0x80;
|
||||
@@ -598,9 +824,51 @@ constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_GS = 0x83;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_GS = 0x87;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_GS = 0x88;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_GS = 0x89;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS = 0x8A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS = 0x8B;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS = 0x8A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_VGPRS_MASK = 0x3F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_SHIFT = 6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_SGPRS_MASK = 0xF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_SHIFT = 10;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_PRIORITY_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FLOAT_MODE_SHIFT = 12;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FLOAT_MODE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DX10_CLAMP_SHIFT = 21;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DX10_CLAMP_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DEBUG_MODE_SHIFT = 22;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_DEBUG_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_IEEE_MODE_SHIFT = 23;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_IEEE_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_CU_GROUP_ENABLE_SHIFT = 24;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_CU_GROUP_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FWD_PROGRESS_SHIFT = 26;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FWD_PROGRESS_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_WGP_MODE_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_WGP_MODE_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_GS_VGPR_COMP_CNT_SHIFT = 29;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_GS_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FP16_OVFL_SHIFT = 31;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS_FP16_OVFL_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS = 0x8B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SCRATCH_EN_SHIFT = 0;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SCRATCH_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_SHIFT = 1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_ES_VGPR_COMP_CNT_SHIFT = 16;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_ES_VGPR_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_OC_LDS_EN_SHIFT = 18;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_OC_LDS_EN_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_LDS_SIZE_SHIFT = 19;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_LDS_SIZE_MASK = 0xFF;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MSB_SHIFT = 27;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_USER_SGPR_MSB_MASK = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_SHIFT = 28;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS_SHARED_VGPR_CNT_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_0 = 0x8C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_15 = 0x9B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0 = 0xB2;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_ES = 0xC8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_ES = 0xC9;
|
||||
@@ -670,24 +938,41 @@ constexpr uint32_t SH_NUM = 0x2FF + 1;
|
||||
|
||||
/* User config registers */
|
||||
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE_PRIM_TYPE_SHIFT = 0;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE_PRIM_TYPE_MASK = 0x3F;
|
||||
|
||||
constexpr uint32_t VGT_OBJECT_ID = 0x248;
|
||||
constexpr uint32_t GE_INDX_OFFSET = 0x24A;
|
||||
constexpr uint32_t GE_MULTI_PRIM_IB_RESET_EN = 0x24B;
|
||||
constexpr uint32_t VGT_HS_OFFCHIP_PARAM = 0x24F;
|
||||
constexpr uint32_t VGT_TF_MEMORY_BASE = 0x250;
|
||||
constexpr uint32_t GE_CNTL = 0x25B;
|
||||
constexpr uint32_t GE_USER_VGPR1 = 0x25C;
|
||||
constexpr uint32_t GE_USER_VGPR2 = 0x25D;
|
||||
constexpr uint32_t GE_USER_VGPR3 = 0x25E;
|
||||
constexpr uint32_t GE_STEREO_CNTL = 0x25F;
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR = 0x380;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR_HI = 0x381;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
|
||||
constexpr uint32_t GDS_OA_CNTL = 0x41D;
|
||||
constexpr uint32_t GDS_OA_COUNTER = 0x41E;
|
||||
constexpr uint32_t GDS_OA_ADDRESS = 0x41F;
|
||||
|
||||
constexpr uint32_t GE_CNTL = 0x25B;
|
||||
constexpr uint32_t GE_CNTL_PRIM_GRP_SIZE_SHIFT = 0;
|
||||
constexpr uint32_t GE_CNTL_PRIM_GRP_SIZE_MASK = 0x1FF;
|
||||
constexpr uint32_t GE_CNTL_VERT_GRP_SIZE_SHIFT = 9;
|
||||
constexpr uint32_t GE_CNTL_VERT_GRP_SIZE_MASK = 0x1FF;
|
||||
|
||||
constexpr uint32_t GE_USER_VGPR1 = 0x25C;
|
||||
constexpr uint32_t GE_USER_VGPR2 = 0x25D;
|
||||
constexpr uint32_t GE_USER_VGPR3 = 0x25E;
|
||||
constexpr uint32_t GE_STEREO_CNTL = 0x25F;
|
||||
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR1_SHIFT = 0;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR1_MASK = 0x1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR2_SHIFT = 1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR2_MASK = 0x1;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_SHIFT = 2;
|
||||
constexpr uint32_t GE_USER_VGPR_EN_EN_USER_VGPR3_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR = 0x380;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR_HI = 0x381;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
|
||||
constexpr uint32_t GDS_OA_CNTL = 0x41D;
|
||||
constexpr uint32_t GDS_OA_COUNTER = 0x41E;
|
||||
constexpr uint32_t GDS_OA_ADDRESS = 0x41F;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
|
||||
@@ -823,6 +823,7 @@ Vector<uint32_t> ShaderRecompileVS(const ShaderCode& code, const ShaderVertexInp
|
||||
Vector<uint32_t> ShaderRecompilePS(const ShaderCode& code, const ShaderPixelInputInfo* input_info);
|
||||
Vector<uint32_t> ShaderRecompileCS(const ShaderCode& code, const ShaderComputeInputInfo* input_info);
|
||||
bool ShaderIsDisabled(uint64_t addr);
|
||||
bool ShaderIsDisabled2(uint64_t addr, uint64_t chksum);
|
||||
void ShaderDisable(uint64_t id);
|
||||
void ShaderInjectDebugPrintf(uint64_t id, const ShaderDebugPrintf& cmd);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user