mirror of
https://github.com/InoriRus/Kyty.git
synced 2026-08-28 05:06:40 +00:00
PS5 graphics (#42)
This commit is contained in:
InoriRus
@@ -14,8 +14,9 @@ class File;
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#define KYTY_PM4_GET(u, r, f) (((u) >> Pm4::r##_##f##_SHIFT) & Pm4::r##_##f##_MASK)
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#define KYTY_PM4(len, op, r) \
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(0xC0000000u | (((static_cast<uint16_t>(len) - 2u) & 0x3fffu) << 16u) | (((op)&0xffu) << 8u) | (((r)&0x3fu) << 2u))
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(0xC0000000u | (((static_cast<uint16_t>(len) - 2u) & 0x3fffu) << 16u) | (((op)&0xffu) << 8u) | (((r) & (Pm4::R_NUM - 1u)) << 2u))
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#define KYTY_PM4_R(cmd_id) (((cmd_id) >> 2u) & (Pm4::R_NUM - 1u))
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#define KYTY_PM4_LEN(cmd_id) ((((cmd_id) >> 16u) & 0x3fffu) + 2u)
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namespace Kyty::Libs::Graphics::Pm4 {
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@@ -69,26 +70,37 @@ constexpr uint32_t IT_WAIT_ON_DE_COUNTER_DIFF = 0x88;
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constexpr uint32_t IT_DISPATCH_DRAW_PREAMBLE = 0x8C;
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constexpr uint32_t IT_DISPATCH_DRAW = 0x8D;
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constexpr uint32_t R_ZERO = 0x00;
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constexpr uint32_t R_VS = 0x01;
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constexpr uint32_t R_PS = 0x02;
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constexpr uint32_t R_DRAW_INDEX = 0x03;
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constexpr uint32_t R_DRAW_INDEX_AUTO = 0x04;
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constexpr uint32_t R_DRAW_RESET = 0x05;
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constexpr uint32_t R_WAIT_FLIP_DONE = 0x06;
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constexpr uint32_t R_CS = 0x07;
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constexpr uint32_t R_DISPATCH_DIRECT = 0x08;
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constexpr uint32_t R_DISPATCH_RESET = 0x09;
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constexpr uint32_t R_DISPATCH_WAIT_MEM = 0x0A;
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constexpr uint32_t R_PUSH_MARKER = 0x0B;
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constexpr uint32_t R_POP_MARKER = 0x0C;
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constexpr uint32_t R_VS_EMBEDDED = 0x0D;
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constexpr uint32_t R_PS_EMBEDDED = 0x0E;
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constexpr uint32_t R_VS_UPDATE = 0x0F;
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constexpr uint32_t R_PS_UPDATE = 0x10;
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constexpr uint32_t R_SH_REGS = 0x11;
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constexpr uint32_t R_CX_REGS = 0x12;
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constexpr uint32_t R_UC_REGS = 0x13;
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/* Custom codes. Implemented via IT_NOP */
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constexpr uint32_t R_ZERO = 0x00;
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constexpr uint32_t R_VS = 0x01;
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constexpr uint32_t R_PS = 0x02;
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constexpr uint32_t R_DRAW_INDEX = 0x03;
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constexpr uint32_t R_DRAW_INDEX_AUTO = 0x04;
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constexpr uint32_t R_DRAW_RESET = 0x05;
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constexpr uint32_t R_WAIT_FLIP_DONE = 0x06;
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constexpr uint32_t R_CS = 0x07;
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constexpr uint32_t R_DISPATCH_DIRECT = 0x08;
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constexpr uint32_t R_DISPATCH_RESET = 0x09;
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constexpr uint32_t R_WAIT_MEM_32 = 0x0A;
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constexpr uint32_t R_PUSH_MARKER = 0x0B;
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constexpr uint32_t R_POP_MARKER = 0x0C;
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constexpr uint32_t R_VS_EMBEDDED = 0x0D;
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constexpr uint32_t R_PS_EMBEDDED = 0x0E;
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constexpr uint32_t R_VS_UPDATE = 0x0F;
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constexpr uint32_t R_PS_UPDATE = 0x10;
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constexpr uint32_t R_SH_REGS_INDIRECT = 0x11;
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constexpr uint32_t R_CX_REGS_INDIRECT = 0x12;
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constexpr uint32_t R_UC_REGS_INDIRECT = 0x13;
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constexpr uint32_t R_ACQUIRE_MEM = 0x14;
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constexpr uint32_t R_WRITE_DATA = 0x15;
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constexpr uint32_t R_WAIT_MEM_64 = 0x16;
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constexpr uint32_t R_FLIP = 0x17;
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constexpr uint32_t R_RELEASE_MEM = 0x18;
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constexpr uint32_t R_NUM = 0x3F + 1;
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/* Context registers */
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constexpr uint32_t DB_RENDER_CONTROL = 0x0;
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constexpr uint32_t DB_RENDER_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT = 0;
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@@ -106,14 +118,21 @@ constexpr uint32_t DB_RENDER_CONTROL_COPY_CENTROID_MASK = 0x1;
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constexpr uint32_t DB_RENDER_CONTROL_COPY_SAMPLE_SHIFT = 8;
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constexpr uint32_t DB_RENDER_CONTROL_COPY_SAMPLE_MASK = 0xF;
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constexpr uint32_t DB_COUNT_CONTROL = 0x1;
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constexpr uint32_t DB_DEPTH_VIEW = 0x2;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_MASK = 0x7FF;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_SHIFT = 13;
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constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_MASK = 0x7FF;
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constexpr uint32_t DB_HTILE_DATA_BASE = 0x5;
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constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
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constexpr uint32_t DB_RENDER_OVERRIDE = 0x3;
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constexpr uint32_t DB_RENDER_OVERRIDE2 = 0x4;
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constexpr uint32_t DB_HTILE_DATA_BASE = 0x5;
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constexpr uint32_t PS_SHADER_SAMPLE_EXCLUSION_MASK = 0x6;
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constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
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constexpr uint32_t DB_DEPTH_BOUNDS_MIN = 0x8;
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constexpr uint32_t DB_DEPTH_BOUNDS_MAX = 0x9;
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constexpr uint32_t DB_STENCIL_CLEAR = 0xA;
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constexpr uint32_t DB_STENCIL_CLEAR_CLEAR_SHIFT = 0;
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@@ -135,6 +154,8 @@ constexpr uint32_t PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK = 0xFFFF;
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constexpr uint32_t PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT = 16;
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constexpr uint32_t PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK = 0xFFFF;
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constexpr uint32_t DB_DFSM_CONTROL = 0xE;
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constexpr uint32_t DB_DEPTH_INFO = 0xF;
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constexpr uint32_t DB_DEPTH_INFO_ADDR5_SWIZZLE_MASK_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_INFO_ADDR5_SWIZZLE_MASK_MASK = 0xF;
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@@ -171,15 +192,10 @@ constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_MASK = 0x7;
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constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_SHIFT = 29;
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constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_MASK = 0x1;
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constexpr uint32_t DB_Z_READ_BASE = 0x12;
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constexpr uint32_t DB_STENCIL_READ_BASE = 0x13;
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constexpr uint32_t DB_Z_WRITE_BASE = 0x14;
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constexpr uint32_t DB_STENCIL_WRITE_BASE = 0x15;
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constexpr uint32_t DB_Z_READ_BASE_HI = 0x1A;
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constexpr uint32_t DB_STENCIL_READ_BASE_HI = 0x1B;
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constexpr uint32_t DB_Z_WRITE_BASE_HI = 0x1C;
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constexpr uint32_t DB_STENCIL_WRITE_BASE_HI = 0x1D;
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constexpr uint32_t DB_HTILE_DATA_BASE_HI = 0x1E;
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constexpr uint32_t DB_Z_READ_BASE = 0x12;
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constexpr uint32_t DB_STENCIL_READ_BASE = 0x13;
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constexpr uint32_t DB_Z_WRITE_BASE = 0x14;
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constexpr uint32_t DB_STENCIL_WRITE_BASE = 0x15;
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constexpr uint32_t DB_DEPTH_SIZE = 0x16;
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constexpr uint32_t DB_DEPTH_SIZE_PITCH_TILE_MAX_SHIFT = 0;
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@@ -191,6 +207,30 @@ constexpr uint32_t DB_DEPTH_SLICE = 0x17;
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constexpr uint32_t DB_DEPTH_SLICE_SLICE_TILE_MAX_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_SLICE_SLICE_TILE_MAX_MASK = 0x3FFFFF;
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constexpr uint32_t DB_Z_READ_BASE_HI = 0x1A;
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constexpr uint32_t DB_STENCIL_READ_BASE_HI = 0x1B;
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constexpr uint32_t DB_Z_WRITE_BASE_HI = 0x1C;
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constexpr uint32_t DB_STENCIL_WRITE_BASE_HI = 0x1D;
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constexpr uint32_t DB_HTILE_DATA_BASE_HI = 0x1E;
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constexpr uint32_t DB_RMI_L2_CACHE_CONTROL = 0x1F;
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constexpr uint32_t TA_BC_BASE_ADDR = 0x20;
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constexpr uint32_t TA_BC_BASE_ADDR_HI = 0x21;
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constexpr uint32_t PA_SC_WINDOW_OFFSET = 0x80;
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constexpr uint32_t PA_SC_WINDOW_SCISSOR_TL = 0x81;
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constexpr uint32_t PA_SC_WINDOW_SCISSOR_BR = 0x82;
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constexpr uint32_t PA_SC_CLIPRECT_RULE = 0x83;
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constexpr uint32_t PA_SC_CLIPRECT_0_TL = 0x84;
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constexpr uint32_t PA_SC_CLIPRECT_0_BR = 0x85;
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constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET = 0x8D;
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constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_X_SHIFT = 0;
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constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_X_MASK = 0x1FF;
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constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_Y_SHIFT = 16;
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constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_Y_MASK = 0x1FF;
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constexpr uint32_t CB_TARGET_MASK = 0x8E;
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constexpr uint32_t CB_SHADER_MASK = 0x8F;
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constexpr uint32_t PA_SC_GENERIC_SCISSOR_TL = 0x90;
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constexpr uint32_t PA_SC_GENERIC_SCISSOR_TL_TL_X_SHIFT = 0;
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constexpr uint32_t PA_SC_GENERIC_SCISSOR_TL_TL_X_MASK = 0x7FFF;
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@@ -205,12 +245,21 @@ constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_X_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_SHIFT = 16;
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constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_MASK = 0x7FFF;
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constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
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constexpr uint32_t CB_BLEND_RED = 0x105;
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constexpr uint32_t CB_BLEND_GREEN = 0x106;
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constexpr uint32_t CB_BLEND_BLUE = 0x107;
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constexpr uint32_t CB_BLEND_ALPHA = 0x108;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL = 0x94;
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constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR = 0x95;
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constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
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constexpr uint32_t PA_SC_VPORT_ZMAX_0 = 0xB5;
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constexpr uint32_t PA_SC_RIGHT_VERT_GRID = 0xE8;
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constexpr uint32_t PA_SC_LEFT_VERT_GRID = 0xE9;
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constexpr uint32_t PA_SC_HORIZ_GRID = 0xEA;
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constexpr uint32_t PA_SC_FOV_WINDOW_LR = 0xEB;
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constexpr uint32_t PA_SC_FOV_WINDOW_TB = 0xEC;
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constexpr uint32_t CB_RMI_GL2_CACHE_CONTROL = 0x104;
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constexpr uint32_t CB_BLEND_RED = 0x105;
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constexpr uint32_t CB_BLEND_GREEN = 0x106;
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constexpr uint32_t CB_BLEND_BLUE = 0x107;
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constexpr uint32_t CB_BLEND_ALPHA = 0x108;
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constexpr uint32_t CB_DCC_CONTROL = 0x109;
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constexpr uint32_t DB_STENCIL_CONTROL = 0x10B;
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constexpr uint32_t DB_STENCIL_CONTROL_STENCILFAIL_SHIFT = 0;
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@@ -246,9 +295,29 @@ constexpr uint32_t DB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK = 0xFF;
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constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_SHIFT = 24;
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constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_MASK = 0xFF;
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constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
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constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
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constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
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constexpr uint32_t PA_CL_VPORT_XOFFSET = 0x110;
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constexpr uint32_t PA_CL_VPORT_YSCALE = 0x111;
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constexpr uint32_t PA_CL_VPORT_YOFFSET = 0x112;
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constexpr uint32_t PA_CL_VPORT_ZSCALE = 0x113;
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constexpr uint32_t PA_CL_VPORT_ZOFFSET = 0x114;
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constexpr uint32_t PA_CL_UCP_0_X = 0x16F;
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constexpr uint32_t PA_CL_UCP_0_Y = 0x170;
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constexpr uint32_t PA_CL_UCP_0_Z = 0x171;
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constexpr uint32_t PA_CL_UCP_0_W = 0x172;
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constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
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constexpr uint32_t SPI_PS_INPUT_CNTL_31 = 0x1B0;
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constexpr uint32_t SPI_VS_OUT_CONFIG = 0x1B1;
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constexpr uint32_t SPI_PS_INPUT_ENA = 0x1B3;
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constexpr uint32_t SPI_PS_INPUT_ADDR = 0x1B4;
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constexpr uint32_t SPI_INTERP_CONTROL_0 = 0x1B5;
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constexpr uint32_t SPI_PS_IN_CONTROL = 0x1B6;
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constexpr uint32_t SPI_BARYC_CNTL = 0x1B8;
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constexpr uint32_t SPI_TMPRING_SIZE = 0x1BA;
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constexpr uint32_t SPI_SHADER_IDX_FORMAT = 0x1C2;
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constexpr uint32_t SPI_SHADER_POS_FORMAT = 0x1C3;
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constexpr uint32_t SPI_SHADER_Z_FORMAT = 0x1C4;
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constexpr uint32_t SPI_SHADER_COL_FORMAT = 0x1C5;
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constexpr uint32_t CB_BLEND0_CONTROL = 0x1E0;
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constexpr uint32_t CB_BLEND0_CONTROL_COLOR_SRCBLEND_SHIFT = 0;
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@@ -268,6 +337,8 @@ constexpr uint32_t CB_BLEND0_CONTROL_SEPARATE_ALPHA_BLEND_MASK = 0x1;
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constexpr uint32_t CB_BLEND0_CONTROL_ENABLE_SHIFT = 30;
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constexpr uint32_t CB_BLEND0_CONTROL_ENABLE_MASK = 0x1;
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constexpr uint32_t GE_MAX_OUTPUT_PER_SUBGROUP = 0x1FF;
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constexpr uint32_t DB_DEPTH_CONTROL = 0x200;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_SHIFT = 0;
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constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_MASK = 0x1;
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@@ -304,12 +375,56 @@ constexpr uint32_t DB_EQAA_INTERPOLATE_COMP_Z_MASK = 0x1;
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constexpr uint32_t DB_EQAA_STATIC_ANCHOR_ASSOCIATIONS_SHIFT = 20;
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constexpr uint32_t DB_EQAA_STATIC_ANCHOR_ASSOCIATIONS_MASK = 0x1;
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constexpr uint32_t DB_SHADER_CONTROL = 0x203;
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constexpr uint32_t DB_SHADER_CONTROL_Z_EXPORT_ENABLE_SHIFT = 0;
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constexpr uint32_t DB_SHADER_CONTROL_Z_EXPORT_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_SHADER_CONTROL_Z_ORDER_SHIFT = 4;
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constexpr uint32_t DB_SHADER_CONTROL_Z_ORDER_MASK = 0x3;
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constexpr uint32_t DB_SHADER_CONTROL_KILL_ENABLE_SHIFT = 6;
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constexpr uint32_t DB_SHADER_CONTROL_KILL_ENABLE_MASK = 0x1;
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constexpr uint32_t DB_SHADER_CONTROL_EXEC_ON_NOOP_SHIFT = 10;
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constexpr uint32_t DB_SHADER_CONTROL_EXEC_ON_NOOP_MASK = 0x1;
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constexpr uint32_t DB_SHADER_CONTROL_CONSERVATIVE_Z_EXPORT_SHIFT = 13;
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constexpr uint32_t DB_SHADER_CONTROL_CONSERVATIVE_Z_EXPORT_MASK = 0x3;
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constexpr uint32_t CB_COLOR_CONTROL = 0x202;
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constexpr uint32_t CB_COLOR_CONTROL_MODE_SHIFT = 4;
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constexpr uint32_t CB_COLOR_CONTROL_MODE_MASK = 0x7;
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constexpr uint32_t CB_COLOR_CONTROL_ROP3_SHIFT = 16;
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constexpr uint32_t CB_COLOR_CONTROL_ROP3_MASK = 0xFF;
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constexpr uint32_t PA_CL_CLIP_CNTL = 0x204;
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constexpr uint32_t PA_CL_CLIP_CNTL_UCP_ENA_SHIFT = 0;
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constexpr uint32_t PA_CL_CLIP_CNTL_UCP_ENA_MASK = 0x3F;
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constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_Y_SCALE_NEG_SHIFT = 13;
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constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_Y_SCALE_NEG_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_MODE_SHIFT = 14;
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constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_MODE_MASK = 0x3;
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constexpr uint32_t PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT = 16;
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constexpr uint32_t PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_UCP_CULL_ONLY_ENA_SHIFT = 17;
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constexpr uint32_t PA_CL_CLIP_CNTL_UCP_CULL_ONLY_ENA_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT = 18;
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constexpr uint32_t PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT = 19;
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constexpr uint32_t PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT = 20;
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constexpr uint32_t PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT = 21;
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constexpr uint32_t PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_DX_RASTERIZATION_KILL_SHIFT = 22;
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constexpr uint32_t PA_CL_CLIP_CNTL_DX_RASTERIZATION_KILL_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_DX_LINEAR_ATTR_CLIP_ENA_SHIFT = 24;
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constexpr uint32_t PA_CL_CLIP_CNTL_DX_LINEAR_ATTR_CLIP_ENA_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_VTE_VPORT_PROVOKE_DISABLE_SHIFT = 25;
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constexpr uint32_t PA_CL_CLIP_CNTL_VTE_VPORT_PROVOKE_DISABLE_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_NEAR_DISABLE_SHIFT = 26;
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constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_NEAR_DISABLE_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_FAR_DISABLE_SHIFT = 27;
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constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_FAR_DISABLE_MASK = 0x1;
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constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_PROG_NEAR_ENA_SHIFT = 28;
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constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_PROG_NEAR_ENA_MASK = 0x1;
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|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL = 0x205;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT = 0;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK = 0x1;
|
||||
@@ -334,10 +449,21 @@ constexpr uint32_t PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK = 0x1;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT = 20;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t PA_CL_VTE_CNTL = 0x206;
|
||||
constexpr uint32_t PA_CL_VS_OUT_CNTL = 0x207;
|
||||
constexpr uint32_t PA_SU_SMALL_PRIM_FILTER_CNTL = 0x20C;
|
||||
constexpr uint32_t PA_CL_OBJPRIM_ID_CNTL = 0x20D;
|
||||
constexpr uint32_t PA_STEREO_CNTL = 0x210;
|
||||
constexpr uint32_t PA_STATE_STEREO_X = 0x211;
|
||||
constexpr uint32_t PA_SU_POINT_SIZE = 0x280;
|
||||
constexpr uint32_t PA_SU_POINT_MINMAX = 0x281;
|
||||
|
||||
constexpr uint32_t PA_SU_LINE_CNTL = 0x282;
|
||||
constexpr uint32_t PA_SU_LINE_CNTL_WIDTH_SHIFT = 0;
|
||||
constexpr uint32_t PA_SU_LINE_CNTL_WIDTH_MASK = 0xFFFF;
|
||||
|
||||
constexpr uint32_t VGT_GS_ONCHIP_CNTL = 0x291;
|
||||
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0 = 0x292;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_MSAA_ENABLE_SHIFT = 0;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_MSAA_ENABLE_MASK = 0x1;
|
||||
@@ -346,7 +472,13 @@ constexpr uint32_t PA_SC_MODE_CNTL_0_VPORT_SCISSOR_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_LINE_STIPPLE_ENABLE_SHIFT = 2;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_LINE_STIPPLE_ENABLE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t VGT_GS_OUT_PRIM_TYPE = 0x29B;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_1 = 0x293;
|
||||
constexpr uint32_t VGT_GS_OUT_PRIM_TYPE = 0x29B;
|
||||
constexpr uint32_t VGT_PRIMITIVEID_EN = 0x2A1;
|
||||
constexpr uint32_t VGT_PRIMITIVEID_RESET = 0x2A3;
|
||||
constexpr uint32_t VGT_DRAW_PAYLOAD_CNTL = 0x2A6;
|
||||
constexpr uint32_t VGT_ESGS_RING_ITEMSIZE = 0x2AB;
|
||||
constexpr uint32_t VGT_REUSE_OFF = 0x2AD;
|
||||
|
||||
constexpr uint32_t DB_HTILE_SURFACE = 0x2AF;
|
||||
constexpr uint32_t DB_HTILE_SURFACE_LINEAR_SHIFT = 0;
|
||||
@@ -364,9 +496,24 @@ constexpr uint32_t DB_HTILE_SURFACE_PREFETCH_HEIGHT_MASK = 0x3F;
|
||||
constexpr uint32_t DB_HTILE_SURFACE_DST_OUTSIDE_ZERO_TO_ONE_SHIFT = 16;
|
||||
constexpr uint32_t DB_HTILE_SURFACE_DST_OUTSIDE_ZERO_TO_ONE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t VGT_SHADER_STAGES_EN = 0x2D5;
|
||||
|
||||
constexpr uint32_t PA_SC_CENTROID_PRIORITY_0 = 0x2F5;
|
||||
constexpr uint32_t DB_SRESULTS_COMPARE_STATE0 = 0x2B0;
|
||||
constexpr uint32_t DB_SRESULTS_COMPARE_STATE1 = 0x2B1;
|
||||
constexpr uint32_t VGT_GS_MAX_VERT_OUT = 0x2CE;
|
||||
constexpr uint32_t GE_NGG_SUBGRP_CNTL = 0x2D3;
|
||||
constexpr uint32_t VGT_TESS_DISTRIBUTION = 0x2D4;
|
||||
constexpr uint32_t VGT_SHADER_STAGES_EN = 0x2D5;
|
||||
constexpr uint32_t VGT_LS_HS_CONFIG = 0x2D6;
|
||||
constexpr uint32_t VGT_TF_PARAM = 0x2DB;
|
||||
constexpr uint32_t DB_ALPHA_TO_MASK = 0x2DC;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x2DE;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_CLAMP = 0x2DF;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_FRONT_SCALE = 0x2E0;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x2E1;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_BACK_SCALE = 0x2E2;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_BACK_OFFSET = 0x2E3;
|
||||
constexpr uint32_t VGT_GS_INSTANCE_CNT = 0x2E4;
|
||||
constexpr uint32_t PA_SC_CENTROID_PRIORITY_0 = 0x2F5;
|
||||
constexpr uint32_t PA_SC_CENTROID_PRIORITY_1 = 0x2F6;
|
||||
|
||||
constexpr uint32_t PA_SC_AA_CONFIG = 0x2F8;
|
||||
constexpr uint32_t PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT = 0;
|
||||
@@ -378,24 +525,52 @@ constexpr uint32_t PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK = 0xF;
|
||||
constexpr uint32_t PA_SC_AA_CONFIG_MSAA_EXPOSED_SAMPLES_SHIFT = 20;
|
||||
constexpr uint32_t PA_SC_AA_CONFIG_MSAA_EXPOSED_SAMPLES_MASK = 0x7;
|
||||
|
||||
constexpr uint32_t PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x2FE;
|
||||
constexpr uint32_t PA_SU_VTX_CNTL = 0x2F9;
|
||||
constexpr uint32_t PA_CL_GB_VERT_CLIP_ADJ = 0x2FA;
|
||||
constexpr uint32_t PA_CL_GB_VERT_DISC_ADJ = 0x2FB;
|
||||
constexpr uint32_t PA_CL_GB_HORZ_CLIP_ADJ = 0x2FC;
|
||||
constexpr uint32_t PA_CL_GB_HORZ_DISC_ADJ = 0x2FD;
|
||||
constexpr uint32_t PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x2FE;
|
||||
constexpr uint32_t PA_SC_AA_MASK_X0Y0_X1Y0 = 0x30E;
|
||||
constexpr uint32_t PA_SC_AA_MASK_X0Y1_X1Y1 = 0x30F;
|
||||
constexpr uint32_t PA_SC_SHADER_CONTROL = 0x310;
|
||||
constexpr uint32_t PA_SC_BINNER_CNTL_0 = 0x311;
|
||||
constexpr uint32_t PA_SC_BINNER_CNTL_1 = 0x312;
|
||||
constexpr uint32_t PA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x313;
|
||||
constexpr uint32_t PA_SC_NGG_MODE_CNTL = 0x314;
|
||||
constexpr uint32_t CB_COLOR0_BASE = 0x318;
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_BASE = 0x318;
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
constexpr uint32_t FSR_RECURSIONS0 = 0x800003FC;
|
||||
constexpr uint32_t FSR_RECURSIONS1 = 0x800003FD;
|
||||
constexpr uint32_t PA_SC_FSR_ENABLE = 0x800003FE;
|
||||
constexpr uint32_t CX_NOP = 0x800003FF;
|
||||
|
||||
constexpr uint32_t CX_NUM = 0x3FF + 1;
|
||||
|
||||
/* Shader registers */
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC4_PS = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_PS = 0x6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_PS = 0x7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_PS = 0x8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_PS = 0x9;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS = 0xA;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT = 0;
|
||||
@@ -411,11 +586,42 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x0;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_0 = 0x4C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_15 = 0x5B;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_0 = 0x4C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_15 = 0x5B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_GS = 0x80;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC4_GS = 0x81;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_GS = 0x82;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_GS = 0x83;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_GS = 0x87;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_GS = 0x88;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_GS = 0x89;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS = 0x8A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS = 0x8B;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_0 = 0x8C;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0 = 0xB2;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_ES = 0xC8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_ES = 0xC9;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_HS = 0x100;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC4_HS = 0x101;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_HS = 0x102;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_HS = 0x103;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_HS = 0x107;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_HS = 0x108;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_HS = 0x109;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS = 0x10A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS = 0x10B;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_HS_0 = 0x10C;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_0 = 0x132;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_LS = 0x148;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_LS = 0x149;
|
||||
constexpr uint32_t COMPUTE_START_X = 0x204;
|
||||
constexpr uint32_t COMPUTE_START_Y = 0x205;
|
||||
constexpr uint32_t COMPUTE_START_Z = 0x206;
|
||||
constexpr uint32_t COMPUTE_PGM_LO = 0x20C;
|
||||
constexpr uint32_t COMPUTE_PGM_HI = 0x20D;
|
||||
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC1 = 0x212;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_SHIFT = 0;
|
||||
@@ -443,14 +649,62 @@ constexpr uint32_t COMPUTE_PGM_RSRC2_TIDIG_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC2_LDS_SIZE_SHIFT = 15;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC2_LDS_SIZE_MASK = 0x1FF;
|
||||
|
||||
constexpr uint32_t COMPUTE_USER_DATA_0 = 0x240;
|
||||
constexpr uint32_t COMPUTE_USER_DATA_15 = 0x24F;
|
||||
constexpr uint32_t COMPUTE_RESOURCE_LIMITS = 0x215;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE0 = 0x216;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE1 = 0x217;
|
||||
constexpr uint32_t COMPUTE_TMPRING_SIZE = 0x218;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE2 = 0x219;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE3 = 0x21A;
|
||||
constexpr uint32_t COMPUTE_USER_ACCUM_0 = 0x224;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC3 = 0x228;
|
||||
constexpr uint32_t COMPUTE_SHADER_CHKSUM = 0x22A;
|
||||
constexpr uint32_t COMPUTE_USER_DATA_0 = 0x240;
|
||||
constexpr uint32_t COMPUTE_USER_DATA_15 = 0x24F;
|
||||
constexpr uint32_t COMPUTE_DISPATCH_TUNNEL = 0x27D;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
constexpr uint32_t SH_NOP = 0x800002FF;
|
||||
|
||||
constexpr uint32_t SH_NUM = 0x2FF + 1;
|
||||
|
||||
/* User config registers */
|
||||
|
||||
constexpr uint32_t GE_CNTL = 0x25b;
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_OBJECT_ID = 0x248;
|
||||
constexpr uint32_t GE_INDX_OFFSET = 0x24A;
|
||||
constexpr uint32_t GE_MULTI_PRIM_IB_RESET_EN = 0x24B;
|
||||
constexpr uint32_t VGT_HS_OFFCHIP_PARAM = 0x24F;
|
||||
constexpr uint32_t VGT_TF_MEMORY_BASE = 0x250;
|
||||
constexpr uint32_t GE_CNTL = 0x25B;
|
||||
constexpr uint32_t GE_USER_VGPR1 = 0x25C;
|
||||
constexpr uint32_t GE_USER_VGPR2 = 0x25D;
|
||||
constexpr uint32_t GE_USER_VGPR3 = 0x25E;
|
||||
constexpr uint32_t GE_STEREO_CNTL = 0x25F;
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR = 0x380;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR_HI = 0x381;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
|
||||
constexpr uint32_t GDS_OA_CNTL = 0x41D;
|
||||
constexpr uint32_t GDS_OA_COUNTER = 0x41E;
|
||||
constexpr uint32_t GDS_OA_ADDRESS = 0x41F;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
constexpr uint32_t FSR_EXTEND_SUBPIXEL_ROUNDING = 0x80003FF4;
|
||||
constexpr uint32_t FSR_ALPHA_VALUE0 = 0x80003FF5;
|
||||
constexpr uint32_t FSR_ALPHA_VALUE1 = 0x80003FF6;
|
||||
constexpr uint32_t FSR_CONTROL_POINT0 = 0x80003FF7;
|
||||
constexpr uint32_t FSR_CONTROL_POINT1 = 0x80003FF8;
|
||||
constexpr uint32_t FSR_CONTROL_POINT2 = 0x80003FF9;
|
||||
constexpr uint32_t FSR_CONTROL_POINT3 = 0x80003FFA;
|
||||
constexpr uint32_t FSR_WINDOW0 = 0x80003FFB;
|
||||
constexpr uint32_t FSR_WINDOW1 = 0x80003FFC;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_CONTROL = 0x80003FFD;
|
||||
constexpr uint32_t MEMORY_MAPPING_MASK = 0x80003FFE;
|
||||
constexpr uint32_t UC_NOP = 0x80003FFF;
|
||||
|
||||
constexpr uint32_t UC_NUM = 0x3FFF + 1;
|
||||
|
||||
void DumpPm4PacketStream(Core::File* file, uint32_t* cmd_buffer, uint32_t start_dw, uint32_t num_dw);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user