mirror of
https://github.com/InoriRus/Kyty.git
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PS5 graphics (#42)
This commit is contained in:
InoriRus
@@ -11,18 +11,14 @@
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namespace Kyty::Libs::Graphics {
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namespace HW {
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struct VsStageRegisters;
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} // namespace HW
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KYTY_SUBSYSTEM_DEFINE(Graphics);
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void GraphicsDbgDumpDcb(const char* type, uint32_t num_dw, uint32_t* cmd_buffer);
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namespace Gen4 {
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int KYTY_SYSV_ABI GraphicsSetVsShader(uint32_t* cmd, uint64_t size, const HW::VsStageRegisters* vs_regs, uint32_t shader_modifier);
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int KYTY_SYSV_ABI GraphicsUpdateVsShader(uint32_t* cmd, uint64_t size, const HW::VsStageRegisters* vs_regs, uint32_t shader_modifier);
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int KYTY_SYSV_ABI GraphicsSetVsShader(uint32_t* cmd, uint64_t size, const uint32_t* vs_regs, uint32_t shader_modifier);
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int KYTY_SYSV_ABI GraphicsUpdateVsShader(uint32_t* cmd, uint64_t size, const uint32_t* vs_regs, uint32_t shader_modifier);
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int KYTY_SYSV_ABI GraphicsSetPsShader(uint32_t* cmd, uint64_t size, const uint32_t* ps_regs);
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int KYTY_SYSV_ABI GraphicsSetPsShader350(uint32_t* cmd, uint64_t size, const uint32_t* ps_regs);
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int KYTY_SYSV_ABI GraphicsUpdatePsShader(uint32_t* cmd, uint64_t size, const uint32_t* ps_regs);
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@@ -76,11 +72,29 @@ namespace Gen5 {
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struct Shader;
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struct CommandBuffer;
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struct ShaderRegister;
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struct Label;
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int KYTY_SYSV_ABI GraphicsInit(uint32_t* state, uint32_t ver);
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void* KYTY_SYSV_ABI GraphicsGetRegisterDefaults2(uint32_t ver);
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void* KYTY_SYSV_ABI GraphicsGetRegisterDefaults2Internal(uint32_t ver);
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int KYTY_SYSV_ABI GraphicsCreateShader(Shader** dst, void* header, const volatile void* code);
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int KYTY_SYSV_ABI GraphicsInit(uint32_t* state, uint32_t ver);
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void* KYTY_SYSV_ABI GraphicsGetRegisterDefaults2(uint32_t ver);
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void* KYTY_SYSV_ABI GraphicsGetRegisterDefaults2Internal(uint32_t ver);
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int KYTY_SYSV_ABI GraphicsCreateShader(Shader** dst, void* header, const volatile void* code);
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int KYTY_SYSV_ABI GraphicsSetCxRegIndirectPatchSetAddress(uint32_t* cmd, const volatile ShaderRegister* regs);
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int KYTY_SYSV_ABI GraphicsSetShRegIndirectPatchSetAddress(uint32_t* cmd, const volatile ShaderRegister* regs);
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int KYTY_SYSV_ABI GraphicsSetUcRegIndirectPatchSetAddress(uint32_t* cmd, const volatile ShaderRegister* regs);
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int KYTY_SYSV_ABI GraphicsSetCxRegIndirectPatchAddRegisters(uint32_t* cmd, uint32_t num_regs);
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int KYTY_SYSV_ABI GraphicsSetShRegIndirectPatchAddRegisters(uint32_t* cmd, uint32_t num_regs);
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int KYTY_SYSV_ABI GraphicsSetUcRegIndirectPatchAddRegisters(uint32_t* cmd, uint32_t num_regs);
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int KYTY_SYSV_ABI GraphicsCreatePrimState(ShaderRegister* cx_regs, ShaderRegister* uc_regs, const Shader* hs, const Shader* gs,
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uint32_t prim_type);
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int KYTY_SYSV_ABI GraphicsCreateInterpolantMapping(ShaderRegister* regs, const Shader* gs, const Shader* ps);
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int KYTY_SYSV_ABI GraphicsGetDataPacketPayloadAddress(uint32_t** addr, uint32_t* cmd, int type);
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int KYTY_SYSV_ABI GraphicsSuspendPoint();
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uint32_t* KYTY_SYSV_ABI GraphicsCbSetShRegisterRangeDirect(CommandBuffer* buf, uint32_t offset, const uint32_t* values,
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uint32_t num_values);
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uint32_t* KYTY_SYSV_ABI GraphicsCbReleaseMem(CommandBuffer* buf, uint8_t action, uint16_t gcr_cntl, uint8_t dst, uint8_t cache_policy,
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const volatile Label* address, uint8_t data_sel, uint64_t data, uint16_t gds_offset,
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uint16_t gds_size, uint8_t interrupt, uint32_t interrupt_ctx_id);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbResetQueue(CommandBuffer* buf, uint32_t op, uint32_t state);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbWaitUntilSafeForRendering(CommandBuffer* buf, uint32_t video_out_handle, uint32_t display_buffer_index);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbSetCxRegistersIndirect(CommandBuffer* buf, const volatile ShaderRegister* regs, uint32_t num_regs);
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@@ -88,20 +102,26 @@ uint32_t* KYTY_SYSV_ABI GraphicsDcbSetShRegistersIndirect(CommandBuffer* buf, co
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uint32_t* KYTY_SYSV_ABI GraphicsDcbSetUcRegistersIndirect(CommandBuffer* buf, const volatile ShaderRegister* regs, uint32_t num_regs);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbSetIndexSize(CommandBuffer* buf, uint8_t index_size, uint8_t cache_policy);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbDrawIndexAuto(CommandBuffer* buf, uint32_t index_count, uint64_t modifier);
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int KYTY_SYSV_ABI GraphicsSetCxRegIndirectPatchSetAddress(uint32_t* cmd, const volatile ShaderRegister* regs);
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int KYTY_SYSV_ABI GraphicsSetShRegIndirectPatchSetAddress(uint32_t* cmd, const volatile ShaderRegister* regs);
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int KYTY_SYSV_ABI GraphicsSetUcRegIndirectPatchSetAddress(uint32_t* cmd, const volatile ShaderRegister* regs);
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int KYTY_SYSV_ABI GraphicsSetCxRegIndirectPatchAddRegisters(uint32_t* cmd, uint32_t num_regs);
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int KYTY_SYSV_ABI GraphicsSetShRegIndirectPatchAddRegisters(uint32_t* cmd, uint32_t num_regs);
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int KYTY_SYSV_ABI GraphicsSetUcRegIndirectPatchAddRegisters(uint32_t* cmd, uint32_t num_regs);
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int KYTY_SYSV_ABI GraphicsCreatePrimState(ShaderRegister* cx_regs, ShaderRegister* uc_regs, const Shader* hs, const Shader* gs,
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uint32_t prim_type);
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int KYTY_SYSV_ABI GraphicsCreateInterpolantMapping(ShaderRegister* regs, const Shader* gs, const Shader* ps);
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uint32_t* KYTY_SYSV_ABI GraphicsCbSetShRegisterRangeDirect(CommandBuffer* buf, uint32_t offset, const uint32_t* values,
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uint32_t num_values);
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int KYTY_SYSV_ABI GraphicsGetDataPacketPayloadAddress(uint32_t** addr, uint32_t* cmd, int type);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbEventWrite(CommandBuffer* buf, uint8_t event_type, const volatile void* address);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbAcquireMem(CommandBuffer* buf, uint8_t engine, uint32_t cb_db_op, uint32_t gcr_cntl,
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const volatile void* base, uint64_t size_bytes, uint32_t poll_cycles);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbWriteData(CommandBuffer* buf, uint8_t dst, uint8_t cache_policy, uint64_t address_or_offset,
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const void* data, uint32_t num_dwords, uint8_t increment, uint8_t write_confirm);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbWaitRegMem(CommandBuffer* buf, uint8_t size, uint8_t compare_function, uint8_t op, uint8_t cache_policy,
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const volatile void* address, uint64_t reference, uint64_t mask, uint32_t poll_cycles);
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uint32_t* KYTY_SYSV_ABI GraphicsDcbSetFlip(CommandBuffer* buf, uint32_t video_out_handle, int32_t display_buffer_index, uint32_t flip_mode,
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int64_t flip_arg);
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} // namespace Gen5
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namespace Gen5Driver {
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struct Packet;
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int KYTY_SYSV_ABI GraphicsDriverSubmitDcb(const Packet* packet);
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} // namespace Gen5Driver
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} // namespace Kyty::Libs::Graphics
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#endif // KYTY_EMU_ENABLED
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@@ -11,8 +11,9 @@
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namespace Kyty::Libs::Graphics {
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namespace HW {
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class HardwareContext;
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class Context;
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class UserConfig;
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class Shader;
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} // namespace HW
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class CommandProcessor;
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@@ -55,7 +56,6 @@ public:
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VulkanCommandPool* GetPool() { return m_pool; }
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[[nodiscard]] bool IsExecute() const { return m_execute; }
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private:
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VulkanCommandPool* m_pool = nullptr;
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uint32_t m_index = static_cast<uint32_t>(-1);
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@@ -67,9 +67,9 @@ private:
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void GraphicsRenderInit();
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void GraphicsRenderCreateContext();
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void GraphicsRenderDrawIndex(uint64_t submit_id, CommandBuffer* buffer, HW::HardwareContext* ctx, HW::UserConfig* ucfg,
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void GraphicsRenderDrawIndex(uint64_t submit_id, CommandBuffer* buffer, HW::Context* ctx, HW::UserConfig* ucfg, HW::Shader* sh_ctx,
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uint32_t index_type_and_size, uint32_t index_count, const void* index_addr, uint32_t flags, uint32_t type);
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void GraphicsRenderDrawIndexAuto(uint64_t submit_id, CommandBuffer* buffer, HW::HardwareContext* ctx, HW::UserConfig* ucfg,
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void GraphicsRenderDrawIndexAuto(uint64_t submit_id, CommandBuffer* buffer, HW::Context* ctx, HW::UserConfig* ucfg, HW::Shader* sh_ctx,
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uint32_t index_count, uint32_t flags);
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void GraphicsRenderWriteAtEndOfPipe64(uint64_t submit_id, CommandBuffer* buffer, uint64_t* dst_gpu_addr, uint64_t value);
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void GraphicsRenderWriteAtEndOfPipeClockCounter(uint64_t submit_id, CommandBuffer* buffer, uint64_t* dst_gpu_addr);
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@@ -88,7 +88,7 @@ void GraphicsRenderWriteAtEndOfPipeWithInterruptWriteBack64(uint64_t submit_id,
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void GraphicsRenderWriteAtEndOfPipeWithInterrupt64(uint64_t submit_id, CommandBuffer* buffer, uint64_t* dst_gpu_addr, uint64_t value);
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void GraphicsRenderWriteAtEndOfPipeWithInterrupt32(uint64_t submit_id, CommandBuffer* buffer, uint32_t* dst_gpu_addr, uint32_t value);
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void GraphicsRenderWriteBack(CommandProcessor* cp);
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void GraphicsRenderDispatchDirect(uint64_t submit_id, CommandBuffer* buffer, HW::HardwareContext* ctx, uint32_t thread_group_x,
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void GraphicsRenderDispatchDirect(uint64_t submit_id, CommandBuffer* buffer, HW::Context* ctx, HW::Shader* sh_ctx, uint32_t thread_group_x,
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uint32_t thread_group_y, uint32_t thread_group_z, uint32_t mode);
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void GraphicsRenderMemoryBarrier(CommandBuffer* buffer);
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void GraphicsRenderRenderTextureBarrier(CommandBuffer* buffer, uint64_t vaddr, uint64_t size);
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@@ -204,18 +204,18 @@ struct RenderControl
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struct ClipControl
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{
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uint32_t user_clip_planes = 0;
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uint32_t user_clip_plane_mode = 0;
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uint32_t clip_space = 0;
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uint32_t vertex_kill_mode = 0;
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uint32_t min_z_clip_enable = 0;
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uint32_t max_z_clip_enable = 0;
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bool user_clip_plane_negate_y = false;
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bool clip_enable = false;
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bool user_clip_plane_cull_only = false;
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bool cull_on_clipping_error_disable = false;
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bool linear_attribute_clip_enable = false;
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bool force_viewport_index_from_vs_enable = false;
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uint8_t user_clip_planes = 0;
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uint8_t user_clip_plane_mode = 0;
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bool dx_clip_space = false;
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bool vertex_kill_any = false;
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bool min_z_clip_disable = false;
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bool max_z_clip_disable = false;
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bool user_clip_plane_negate_y = false;
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bool clip_disable = false;
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bool user_clip_plane_cull_only = false;
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bool cull_on_clipping_error_disable = false;
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bool linear_attribute_clip_enable = false;
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bool force_viewport_index_from_vs_enable = false;
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};
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struct DepthControl
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@@ -318,6 +318,16 @@ struct AaSampleControl
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uint32_t locations[16] = {};
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};
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struct DepthShaderControl
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{
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uint32_t other_bits = 0;
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uint8_t conservative_z_export_value = 0;
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uint8_t shader_z_behavior = 0;
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bool shader_kill_enable = false;
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bool shader_z_export_enable = false;
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bool shader_execute_on_noop = false;
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};
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struct AaConfig
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{
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uint8_t msaa_num_samples = 0;
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@@ -371,10 +381,6 @@ struct VsStageRegisters
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uint32_t m_spiShaderPgmRsrc1Vs = 0;
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uint32_t m_spiShaderPgmRsrc2Vs = 0;
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uint32_t m_spiVsOutConfig = 0;
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uint32_t m_spiShaderPosFormat = 0;
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uint32_t m_paClVsOutCntl = 0;
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[[nodiscard]] uint64_t GetGpuAddress() const;
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[[nodiscard]] bool GetStreamoutEnabled() const;
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[[nodiscard]] uint32_t GetSgprCount() const;
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@@ -385,26 +391,12 @@ struct VsStageRegisters
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struct PsStageRegisters
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{
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uint64_t data_addr = 0;
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t scratch_en = 0;
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uint8_t user_sgpr = 0;
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uint8_t wave_cnt_en = 0;
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uint32_t shader_z_format = 0;
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uint8_t target_output_mode[8] = {};
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uint32_t ps_input_ena = 0;
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uint32_t ps_input_addr = 0;
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uint32_t ps_in_control = 0;
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uint32_t baryc_cntl = 0;
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uint8_t conservative_z_export_value = 0;
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uint8_t shader_z_behavior = 0;
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bool shader_kill_enable = false;
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bool shader_z_export_enable = false;
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bool shader_execute_on_noop = false;
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uint32_t m_cbShaderMask = 0;
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uint64_t data_addr = 0;
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uint8_t vgprs = 0;
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uint8_t sgprs = 0;
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uint8_t scratch_en = 0;
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uint8_t user_sgpr = 0;
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uint8_t wave_cnt_en = 0;
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};
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struct CsStageRegisters
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@@ -427,6 +419,42 @@ struct CsStageRegisters
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uint8_t lds_size = 0;
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};
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struct ShaderRegisters
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{
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uint32_t m_spiVsOutConfig = 0;
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uint32_t m_spiShaderPosFormat = 0;
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uint32_t m_paClVsOutCntl = 0;
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uint32_t ps_interpolator_settings[32] = {0};
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// uint32_t ps_input_num = 0;
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uint32_t m_spiShaderIdxFormat = 0;
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uint32_t m_geNggSubgrpCntl = 0;
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uint32_t m_vgtGsInstanceCnt = 0;
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uint32_t m_vgtGsOnchipCntl = 0;
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uint32_t m_geMaxOutputPerSubgroup = 0;
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uint32_t m_vgtEsgsRingItemsize = 0;
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uint32_t m_vgtGsMaxVertOut = 0;
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uint32_t m_vgtGsOutPrimType = 0;
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uint32_t shader_z_format = 0;
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uint8_t target_output_mode[8] = {};
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uint32_t ps_input_ena = 0;
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uint32_t ps_input_addr = 0;
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uint32_t ps_in_control = 0;
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uint32_t baryc_cntl = 0;
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uint32_t m_cbShaderMask = 0;
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uint32_t m_paScShaderControl = 0;
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DepthShaderControl db_shader_control;
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[[nodiscard]] uint32_t GetExportCount() const { return 1u + ((m_spiVsOutConfig >> 1u) & 0x1Fu); }
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[[nodiscard]] uint32_t GetEsVertsPerSubgrp() const { return (m_vgtGsOnchipCntl >> 0u) & 0x7FFu; }
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[[nodiscard]] uint32_t GetGsPrimsPerSubgrp() const { return (m_vgtGsOnchipCntl >> 11u) & 0x7FFu; }
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[[nodiscard]] uint32_t GetGsInstPrimsInSubgrp() const { return (m_vgtGsOnchipCntl >> 22u) & 0x3FFu; }
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};
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enum class UserSgprType
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{
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Unknown,
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@@ -453,8 +481,6 @@ struct VertexShaderInfo
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struct PixelShaderInfo
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{
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PsStageRegisters ps_regs;
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uint32_t ps_interpolator_settings[32] = {0};
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uint32_t ps_input_num = 0;
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UserSgprInfo ps_user_sgpr;
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uint32_t ps_embedded_id = 0;
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bool ps_embedded = false;
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@@ -467,15 +493,15 @@ struct ComputeShaderInfo
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UserSgprInfo cs_user_sgpr;
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};
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class HardwareContext
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class Context
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{
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public:
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HardwareContext() = default;
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virtual ~HardwareContext() = default;
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Context() = default;
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virtual ~Context() = default;
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KYTY_CLASS_DEFAULT_COPY(HardwareContext);
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KYTY_CLASS_DEFAULT_COPY(Context);
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void Reset() { *this = HardwareContext(); }
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void Reset() { *this = Context(); }
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void SetColorBase(uint32_t slot, const ColorBase& base) { m_render_targets[slot].base = base; }
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void SetColorPitch(uint32_t slot, const ColorPitch& pitch) { m_render_targets[slot].pitch = pitch; }
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@@ -554,56 +580,6 @@ public:
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}
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[[nodiscard]] const ScreenViewport& GetScreenViewport() const { return m_screen_viewport; }
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void SetVsShader(const VsStageRegisters* vs_regs, uint32_t shader_modifier)
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{
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m_vs.vs_regs = *vs_regs;
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m_vs.vs_shader_modifier = shader_modifier;
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m_vs.vs_embedded = false;
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}
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void UpdateVsShader(const VsStageRegisters* vs_regs, uint32_t shader_modifier)
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{
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m_vs.vs_regs.m_spiShaderPgmLoVs = vs_regs->m_spiShaderPgmLoVs;
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m_vs.vs_regs.m_spiShaderPgmHiVs = vs_regs->m_spiShaderPgmHiVs;
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m_vs.vs_regs.m_spiShaderPgmRsrc1Vs = vs_regs->m_spiShaderPgmRsrc1Vs;
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m_vs.vs_regs.m_spiShaderPgmRsrc2Vs = vs_regs->m_spiShaderPgmRsrc2Vs;
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m_vs.vs_shader_modifier = shader_modifier;
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m_vs.vs_embedded = false;
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}
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void SetVsEmbedded(uint32_t id, uint32_t shader_modifier)
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{
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m_vs.vs_embedded_id = id;
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m_vs.vs_shader_modifier = shader_modifier;
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m_vs.vs_embedded = true;
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}
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void SetPsShader(const PsStageRegisters* ps_regs)
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{
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m_ps.ps_regs = *ps_regs;
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m_ps.ps_embedded = false;
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}
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void UpdatePsShader(const PsStageRegisters* ps_regs)
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{
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m_ps.ps_regs.data_addr = ps_regs->data_addr;
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m_ps.ps_regs.vgprs = ps_regs->vgprs;
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m_ps.ps_regs.sgprs = ps_regs->sgprs;
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m_ps.ps_regs.scratch_en = ps_regs->scratch_en;
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m_ps.ps_regs.user_sgpr = ps_regs->user_sgpr;
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m_ps.ps_regs.wave_cnt_en = ps_regs->wave_cnt_en;
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m_ps.ps_regs.shader_z_format = ps_regs->shader_z_format;
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m_ps.ps_embedded = false;
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}
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void SetPsEmbedded(uint32_t id)
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||||
{
|
||||
m_ps.ps_embedded_id = id;
|
||||
m_ps.ps_embedded = true;
|
||||
}
|
||||
|
||||
void SetCsShader(const CsStageRegisters* cs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
m_cs.cs_regs = *cs_regs;
|
||||
m_cs.cs_shader_modifier = shader_modifier;
|
||||
}
|
||||
|
||||
[[nodiscard]] const BlendColor& GetBlendColor() const { return m_blend_color; }
|
||||
void SetBlendColor(const BlendColor& color) { m_blend_color = color; }
|
||||
[[nodiscard]] const ClipControl& GetClipControl() const { return m_clip_control; }
|
||||
@@ -629,6 +605,153 @@ public:
|
||||
[[nodiscard]] const AaConfig& GetAaConfig() const { return m_aa_config; }
|
||||
void SetAaConfig(const AaConfig& config) { m_aa_config = config; }
|
||||
|
||||
[[nodiscard]] float GetDepthClearValue() const { return m_depth_clear_value; }
|
||||
void SetDepthClearValue(float clear_value) { m_depth_clear_value = clear_value; }
|
||||
[[nodiscard]] uint8_t GetStencilClearValue() const { return m_stencil_clear_value; }
|
||||
void SetStencilClearValue(uint8_t clear_value) { m_stencil_clear_value = clear_value; }
|
||||
|
||||
[[nodiscard]] float GetLineWidth() const { return m_line_width; }
|
||||
void SetLineWidth(float width) { m_line_width = width; }
|
||||
|
||||
[[nodiscard]] const ShaderRegisters& GetShaderRegisters() const { return m_sh_regs; }
|
||||
|
||||
void SetVsOutConfig(uint32_t value) { m_sh_regs.m_spiVsOutConfig = value; }
|
||||
void SetShaderPosFormat(uint32_t value) { m_sh_regs.m_spiShaderPosFormat = value; }
|
||||
void SetClVsOutCntl(uint32_t value) { m_sh_regs.m_paClVsOutCntl = value; }
|
||||
void SetShaderIdxFormat(uint32_t value) { m_sh_regs.m_spiShaderIdxFormat = value; }
|
||||
void SetNggSubgrpCntl(uint32_t value) { m_sh_regs.m_geNggSubgrpCntl = value; }
|
||||
void SetGsInstanceCnt(uint32_t value) { m_sh_regs.m_vgtGsInstanceCnt = value; }
|
||||
void SetGsOnchipCntl(uint32_t value) { m_sh_regs.m_vgtGsOnchipCntl = value; }
|
||||
void SetMaxOutputPerSubgroup(uint32_t value) { m_sh_regs.m_geMaxOutputPerSubgroup = value; }
|
||||
void SetEsgsRingItemsize(uint32_t value) { m_sh_regs.m_vgtEsgsRingItemsize = value; }
|
||||
void SetGsMaxVertOut(uint32_t value) { m_sh_regs.m_vgtGsMaxVertOut = value; }
|
||||
void SetGsOutPrimType(uint32_t value) { m_sh_regs.m_vgtGsOutPrimType = value; }
|
||||
|
||||
void SetPsInputSettings(uint32_t id, uint32_t value)
|
||||
{
|
||||
m_sh_regs.ps_interpolator_settings[id] = value;
|
||||
// m_sh_regs.ps_input_num = ((id + 1) > m_sh_regs.ps_input_num ? (id + 1) : m_sh_regs.ps_input_num);
|
||||
}
|
||||
|
||||
void SetShaderZFormat(uint32_t value) { m_sh_regs.shader_z_format = value; }
|
||||
void SetTargetOutputMode(uint32_t slot, uint8_t value) { m_sh_regs.target_output_mode[slot] = value; }
|
||||
void SetPsInputEna(uint32_t value) { m_sh_regs.ps_input_ena = value; }
|
||||
void SetPsInputAddr(uint32_t value) { m_sh_regs.ps_input_addr = value; }
|
||||
void SetPsInControl(uint32_t value) { m_sh_regs.ps_in_control = value; }
|
||||
void SetBarycCntl(uint32_t value) { m_sh_regs.baryc_cntl = value; }
|
||||
void SetShaderMask(uint32_t value) { m_sh_regs.m_cbShaderMask = value; }
|
||||
void SetDepthShaderControl(const DepthShaderControl& value) { m_sh_regs.db_shader_control = value; }
|
||||
|
||||
void SetScShaderControl(uint32_t value) { m_sh_regs.m_paScShaderControl = value; }
|
||||
|
||||
private:
|
||||
float m_line_width = 1.0f;
|
||||
|
||||
BlendControl m_blend_control[8];
|
||||
BlendColor m_blend_color;
|
||||
RenderTarget m_render_targets[8];
|
||||
uint32_t m_render_target_mask = 0;
|
||||
ScreenViewport m_screen_viewport;
|
||||
ClipControl m_clip_control;
|
||||
ColorControl m_color_control;
|
||||
ScanModeControl m_scan_mode_control;
|
||||
|
||||
AaSampleControl m_aa_sample_control;
|
||||
AaConfig m_aa_config;
|
||||
|
||||
uint32_t m_shader_stages = 0;
|
||||
|
||||
DepthRenderTarget m_depth_render_target;
|
||||
RenderControl m_render_control;
|
||||
DepthControl m_depth_control;
|
||||
StencilControl m_stencil_control;
|
||||
StencilMask m_stencil_mask;
|
||||
float m_depth_clear_value = 0.0f;
|
||||
uint8_t m_stencil_clear_value = 0;
|
||||
|
||||
ModeControl m_mode_control;
|
||||
EqaaControl m_eqaa_control;
|
||||
|
||||
ShaderRegisters m_sh_regs;
|
||||
};
|
||||
|
||||
class UserConfig
|
||||
{
|
||||
public:
|
||||
UserConfig() = default;
|
||||
virtual ~UserConfig() = default;
|
||||
|
||||
KYTY_CLASS_DEFAULT_COPY(UserConfig);
|
||||
|
||||
void Reset() { *this = UserConfig(); }
|
||||
|
||||
void SetPrimitiveType(uint32_t prim_type) { m_prim_type = prim_type; }
|
||||
[[nodiscard]] uint32_t GetPrimType() const { return m_prim_type; }
|
||||
|
||||
private:
|
||||
uint32_t m_prim_type = 0;
|
||||
};
|
||||
|
||||
class Shader
|
||||
{
|
||||
public:
|
||||
Shader() = default;
|
||||
virtual ~Shader() = default;
|
||||
|
||||
KYTY_CLASS_DEFAULT_COPY(Shader);
|
||||
|
||||
void Reset() { *this = Shader(); }
|
||||
|
||||
void SetVsShader(const VsStageRegisters& vs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
m_vs.vs_regs = vs_regs;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
|
||||
void UpdateVsShader(const VsStageRegisters& vs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
m_vs.vs_regs.m_spiShaderPgmLoVs = vs_regs.m_spiShaderPgmLoVs;
|
||||
m_vs.vs_regs.m_spiShaderPgmHiVs = vs_regs.m_spiShaderPgmHiVs;
|
||||
m_vs.vs_regs.m_spiShaderPgmRsrc1Vs = vs_regs.m_spiShaderPgmRsrc1Vs;
|
||||
m_vs.vs_regs.m_spiShaderPgmRsrc2Vs = vs_regs.m_spiShaderPgmRsrc2Vs;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = false;
|
||||
}
|
||||
void SetVsEmbedded(uint32_t id, uint32_t shader_modifier)
|
||||
{
|
||||
m_vs.vs_embedded_id = id;
|
||||
m_vs.vs_shader_modifier = shader_modifier;
|
||||
m_vs.vs_embedded = true;
|
||||
}
|
||||
|
||||
void SetPsShader(const PsStageRegisters& ps_regs)
|
||||
{
|
||||
m_ps.ps_regs = ps_regs;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void UpdatePsShader(const PsStageRegisters& ps_regs)
|
||||
{
|
||||
m_ps.ps_regs.data_addr = ps_regs.data_addr;
|
||||
m_ps.ps_regs.vgprs = ps_regs.vgprs;
|
||||
m_ps.ps_regs.sgprs = ps_regs.sgprs;
|
||||
m_ps.ps_regs.scratch_en = ps_regs.scratch_en;
|
||||
m_ps.ps_regs.user_sgpr = ps_regs.user_sgpr;
|
||||
m_ps.ps_regs.wave_cnt_en = ps_regs.wave_cnt_en;
|
||||
m_ps.ps_embedded = false;
|
||||
}
|
||||
void SetPsEmbedded(uint32_t id)
|
||||
{
|
||||
m_ps.ps_embedded_id = id;
|
||||
m_ps.ps_embedded = true;
|
||||
}
|
||||
|
||||
void SetCsShader(const CsStageRegisters& cs_regs, uint32_t shader_modifier)
|
||||
{
|
||||
m_cs.cs_regs = cs_regs;
|
||||
m_cs.cs_shader_modifier = shader_modifier;
|
||||
}
|
||||
|
||||
void SetVsUserSgpr(uint32_t id, uint32_t value, UserSgprType type)
|
||||
{
|
||||
m_vs.vs_user_sgpr.value[id] = value;
|
||||
@@ -647,71 +770,15 @@ public:
|
||||
m_cs.cs_user_sgpr.type[id] = type;
|
||||
m_cs.cs_user_sgpr.count = ((id + 1) > m_cs.cs_user_sgpr.count ? (id + 1) : m_cs.cs_user_sgpr.count);
|
||||
}
|
||||
void SetPsInputSettings(uint32_t id, uint32_t value)
|
||||
{
|
||||
m_ps.ps_interpolator_settings[id] = value;
|
||||
m_ps.ps_input_num = ((id + 1) > m_ps.ps_input_num ? (id + 1) : m_ps.ps_input_num);
|
||||
}
|
||||
|
||||
[[nodiscard]] const PixelShaderInfo& GetPs() const { return m_ps; }
|
||||
[[nodiscard]] const VertexShaderInfo& GetVs() const { return m_vs; }
|
||||
[[nodiscard]] const ComputeShaderInfo& GetCs() const { return m_cs; }
|
||||
|
||||
[[nodiscard]] float GetDepthClearValue() const { return m_depth_clear_value; }
|
||||
void SetDepthClearValue(float clear_value) { m_depth_clear_value = clear_value; }
|
||||
[[nodiscard]] uint8_t GetStencilClearValue() const { return m_stencil_clear_value; }
|
||||
void SetStencilClearValue(uint8_t clear_value) { m_stencil_clear_value = clear_value; }
|
||||
|
||||
[[nodiscard]] float GetLineWidth() const { return m_line_width; }
|
||||
void SetLineWidth(float width) { m_line_width = width; }
|
||||
|
||||
private:
|
||||
float m_line_width = 1.0f;
|
||||
|
||||
BlendControl m_blend_control[8];
|
||||
BlendColor m_blend_color;
|
||||
RenderTarget m_render_targets[8];
|
||||
uint32_t m_render_target_mask = 0;
|
||||
ScreenViewport m_screen_viewport;
|
||||
ClipControl m_clip_control;
|
||||
ColorControl m_color_control;
|
||||
ScanModeControl m_scan_mode_control;
|
||||
|
||||
AaSampleControl m_aa_sample_control;
|
||||
AaConfig m_aa_config;
|
||||
|
||||
VertexShaderInfo m_vs;
|
||||
PixelShaderInfo m_ps;
|
||||
ComputeShaderInfo m_cs;
|
||||
uint32_t m_shader_stages = 0;
|
||||
|
||||
DepthRenderTarget m_depth_render_target;
|
||||
RenderControl m_render_control;
|
||||
DepthControl m_depth_control;
|
||||
StencilControl m_stencil_control;
|
||||
StencilMask m_stencil_mask;
|
||||
float m_depth_clear_value = 0.0f;
|
||||
uint8_t m_stencil_clear_value = 0;
|
||||
|
||||
ModeControl m_mode_control;
|
||||
EqaaControl m_eqaa_control;
|
||||
};
|
||||
|
||||
class UserConfig
|
||||
{
|
||||
public:
|
||||
UserConfig() = default;
|
||||
virtual ~UserConfig() = default;
|
||||
|
||||
KYTY_CLASS_DEFAULT_COPY(UserConfig);
|
||||
|
||||
void Reset() { *this = UserConfig(); }
|
||||
|
||||
void SetPrimitiveType(uint32_t prim_type) { m_prim_type = prim_type; }
|
||||
[[nodiscard]] uint32_t GetPrimType() const { return m_prim_type; }
|
||||
|
||||
private:
|
||||
uint32_t m_prim_type = 0;
|
||||
};
|
||||
|
||||
inline uint64_t VsStageRegisters::GetGpuAddress() const
|
||||
|
||||
@@ -14,8 +14,9 @@ class File;
|
||||
#define KYTY_PM4_GET(u, r, f) (((u) >> Pm4::r##_##f##_SHIFT) & Pm4::r##_##f##_MASK)
|
||||
|
||||
#define KYTY_PM4(len, op, r) \
|
||||
(0xC0000000u | (((static_cast<uint16_t>(len) - 2u) & 0x3fffu) << 16u) | (((op)&0xffu) << 8u) | (((r)&0x3fu) << 2u))
|
||||
(0xC0000000u | (((static_cast<uint16_t>(len) - 2u) & 0x3fffu) << 16u) | (((op)&0xffu) << 8u) | (((r) & (Pm4::R_NUM - 1u)) << 2u))
|
||||
|
||||
#define KYTY_PM4_R(cmd_id) (((cmd_id) >> 2u) & (Pm4::R_NUM - 1u))
|
||||
#define KYTY_PM4_LEN(cmd_id) ((((cmd_id) >> 16u) & 0x3fffu) + 2u)
|
||||
|
||||
namespace Kyty::Libs::Graphics::Pm4 {
|
||||
@@ -69,26 +70,37 @@ constexpr uint32_t IT_WAIT_ON_DE_COUNTER_DIFF = 0x88;
|
||||
constexpr uint32_t IT_DISPATCH_DRAW_PREAMBLE = 0x8C;
|
||||
constexpr uint32_t IT_DISPATCH_DRAW = 0x8D;
|
||||
|
||||
constexpr uint32_t R_ZERO = 0x00;
|
||||
constexpr uint32_t R_VS = 0x01;
|
||||
constexpr uint32_t R_PS = 0x02;
|
||||
constexpr uint32_t R_DRAW_INDEX = 0x03;
|
||||
constexpr uint32_t R_DRAW_INDEX_AUTO = 0x04;
|
||||
constexpr uint32_t R_DRAW_RESET = 0x05;
|
||||
constexpr uint32_t R_WAIT_FLIP_DONE = 0x06;
|
||||
constexpr uint32_t R_CS = 0x07;
|
||||
constexpr uint32_t R_DISPATCH_DIRECT = 0x08;
|
||||
constexpr uint32_t R_DISPATCH_RESET = 0x09;
|
||||
constexpr uint32_t R_DISPATCH_WAIT_MEM = 0x0A;
|
||||
constexpr uint32_t R_PUSH_MARKER = 0x0B;
|
||||
constexpr uint32_t R_POP_MARKER = 0x0C;
|
||||
constexpr uint32_t R_VS_EMBEDDED = 0x0D;
|
||||
constexpr uint32_t R_PS_EMBEDDED = 0x0E;
|
||||
constexpr uint32_t R_VS_UPDATE = 0x0F;
|
||||
constexpr uint32_t R_PS_UPDATE = 0x10;
|
||||
constexpr uint32_t R_SH_REGS = 0x11;
|
||||
constexpr uint32_t R_CX_REGS = 0x12;
|
||||
constexpr uint32_t R_UC_REGS = 0x13;
|
||||
/* Custom codes. Implemented via IT_NOP */
|
||||
|
||||
constexpr uint32_t R_ZERO = 0x00;
|
||||
constexpr uint32_t R_VS = 0x01;
|
||||
constexpr uint32_t R_PS = 0x02;
|
||||
constexpr uint32_t R_DRAW_INDEX = 0x03;
|
||||
constexpr uint32_t R_DRAW_INDEX_AUTO = 0x04;
|
||||
constexpr uint32_t R_DRAW_RESET = 0x05;
|
||||
constexpr uint32_t R_WAIT_FLIP_DONE = 0x06;
|
||||
constexpr uint32_t R_CS = 0x07;
|
||||
constexpr uint32_t R_DISPATCH_DIRECT = 0x08;
|
||||
constexpr uint32_t R_DISPATCH_RESET = 0x09;
|
||||
constexpr uint32_t R_WAIT_MEM_32 = 0x0A;
|
||||
constexpr uint32_t R_PUSH_MARKER = 0x0B;
|
||||
constexpr uint32_t R_POP_MARKER = 0x0C;
|
||||
constexpr uint32_t R_VS_EMBEDDED = 0x0D;
|
||||
constexpr uint32_t R_PS_EMBEDDED = 0x0E;
|
||||
constexpr uint32_t R_VS_UPDATE = 0x0F;
|
||||
constexpr uint32_t R_PS_UPDATE = 0x10;
|
||||
constexpr uint32_t R_SH_REGS_INDIRECT = 0x11;
|
||||
constexpr uint32_t R_CX_REGS_INDIRECT = 0x12;
|
||||
constexpr uint32_t R_UC_REGS_INDIRECT = 0x13;
|
||||
constexpr uint32_t R_ACQUIRE_MEM = 0x14;
|
||||
constexpr uint32_t R_WRITE_DATA = 0x15;
|
||||
constexpr uint32_t R_WAIT_MEM_64 = 0x16;
|
||||
constexpr uint32_t R_FLIP = 0x17;
|
||||
constexpr uint32_t R_RELEASE_MEM = 0x18;
|
||||
|
||||
constexpr uint32_t R_NUM = 0x3F + 1;
|
||||
|
||||
/* Context registers */
|
||||
|
||||
constexpr uint32_t DB_RENDER_CONTROL = 0x0;
|
||||
constexpr uint32_t DB_RENDER_CONTROL_DEPTH_CLEAR_ENABLE_SHIFT = 0;
|
||||
@@ -106,14 +118,21 @@ constexpr uint32_t DB_RENDER_CONTROL_COPY_CENTROID_MASK = 0x1;
|
||||
constexpr uint32_t DB_RENDER_CONTROL_COPY_SAMPLE_SHIFT = 8;
|
||||
constexpr uint32_t DB_RENDER_CONTROL_COPY_SAMPLE_MASK = 0xF;
|
||||
|
||||
constexpr uint32_t DB_COUNT_CONTROL = 0x1;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_VIEW = 0x2;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_START_MASK = 0x7FF;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_SHIFT = 13;
|
||||
constexpr uint32_t DB_DEPTH_VIEW_SLICE_MAX_MASK = 0x7FF;
|
||||
|
||||
constexpr uint32_t DB_HTILE_DATA_BASE = 0x5;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
|
||||
constexpr uint32_t DB_RENDER_OVERRIDE = 0x3;
|
||||
constexpr uint32_t DB_RENDER_OVERRIDE2 = 0x4;
|
||||
constexpr uint32_t DB_HTILE_DATA_BASE = 0x5;
|
||||
constexpr uint32_t PS_SHADER_SAMPLE_EXCLUSION_MASK = 0x6;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_XY = 0x7;
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MIN = 0x8;
|
||||
constexpr uint32_t DB_DEPTH_BOUNDS_MAX = 0x9;
|
||||
|
||||
constexpr uint32_t DB_STENCIL_CLEAR = 0xA;
|
||||
constexpr uint32_t DB_STENCIL_CLEAR_CLEAR_SHIFT = 0;
|
||||
@@ -135,6 +154,8 @@ constexpr uint32_t PA_SC_SCREEN_SCISSOR_BR_BR_X_MASK = 0xFFFF;
|
||||
constexpr uint32_t PA_SC_SCREEN_SCISSOR_BR_BR_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SC_SCREEN_SCISSOR_BR_BR_Y_MASK = 0xFFFF;
|
||||
|
||||
constexpr uint32_t DB_DFSM_CONTROL = 0xE;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_INFO = 0xF;
|
||||
constexpr uint32_t DB_DEPTH_INFO_ADDR5_SWIZZLE_MASK_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_INFO_ADDR5_SWIZZLE_MASK_MASK = 0xF;
|
||||
@@ -171,15 +192,10 @@ constexpr uint32_t DB_STENCIL_INFO_TILE_MODE_INDEX_MASK = 0x7;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_SHIFT = 29;
|
||||
constexpr uint32_t DB_STENCIL_INFO_TILE_STENCIL_DISABLE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t DB_Z_READ_BASE = 0x12;
|
||||
constexpr uint32_t DB_STENCIL_READ_BASE = 0x13;
|
||||
constexpr uint32_t DB_Z_WRITE_BASE = 0x14;
|
||||
constexpr uint32_t DB_STENCIL_WRITE_BASE = 0x15;
|
||||
constexpr uint32_t DB_Z_READ_BASE_HI = 0x1A;
|
||||
constexpr uint32_t DB_STENCIL_READ_BASE_HI = 0x1B;
|
||||
constexpr uint32_t DB_Z_WRITE_BASE_HI = 0x1C;
|
||||
constexpr uint32_t DB_STENCIL_WRITE_BASE_HI = 0x1D;
|
||||
constexpr uint32_t DB_HTILE_DATA_BASE_HI = 0x1E;
|
||||
constexpr uint32_t DB_Z_READ_BASE = 0x12;
|
||||
constexpr uint32_t DB_STENCIL_READ_BASE = 0x13;
|
||||
constexpr uint32_t DB_Z_WRITE_BASE = 0x14;
|
||||
constexpr uint32_t DB_STENCIL_WRITE_BASE = 0x15;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_SIZE = 0x16;
|
||||
constexpr uint32_t DB_DEPTH_SIZE_PITCH_TILE_MAX_SHIFT = 0;
|
||||
@@ -191,6 +207,30 @@ constexpr uint32_t DB_DEPTH_SLICE = 0x17;
|
||||
constexpr uint32_t DB_DEPTH_SLICE_SLICE_TILE_MAX_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_SLICE_SLICE_TILE_MAX_MASK = 0x3FFFFF;
|
||||
|
||||
constexpr uint32_t DB_Z_READ_BASE_HI = 0x1A;
|
||||
constexpr uint32_t DB_STENCIL_READ_BASE_HI = 0x1B;
|
||||
constexpr uint32_t DB_Z_WRITE_BASE_HI = 0x1C;
|
||||
constexpr uint32_t DB_STENCIL_WRITE_BASE_HI = 0x1D;
|
||||
constexpr uint32_t DB_HTILE_DATA_BASE_HI = 0x1E;
|
||||
constexpr uint32_t DB_RMI_L2_CACHE_CONTROL = 0x1F;
|
||||
constexpr uint32_t TA_BC_BASE_ADDR = 0x20;
|
||||
constexpr uint32_t TA_BC_BASE_ADDR_HI = 0x21;
|
||||
constexpr uint32_t PA_SC_WINDOW_OFFSET = 0x80;
|
||||
constexpr uint32_t PA_SC_WINDOW_SCISSOR_TL = 0x81;
|
||||
constexpr uint32_t PA_SC_WINDOW_SCISSOR_BR = 0x82;
|
||||
constexpr uint32_t PA_SC_CLIPRECT_RULE = 0x83;
|
||||
constexpr uint32_t PA_SC_CLIPRECT_0_TL = 0x84;
|
||||
constexpr uint32_t PA_SC_CLIPRECT_0_BR = 0x85;
|
||||
|
||||
constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET = 0x8D;
|
||||
constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_X_SHIFT = 0;
|
||||
constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_X_MASK = 0x1FF;
|
||||
constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SU_HARDWARE_SCREEN_OFFSET_HW_SCREEN_OFFSET_Y_MASK = 0x1FF;
|
||||
|
||||
constexpr uint32_t CB_TARGET_MASK = 0x8E;
|
||||
constexpr uint32_t CB_SHADER_MASK = 0x8F;
|
||||
|
||||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_TL = 0x90;
|
||||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_TL_TL_X_SHIFT = 0;
|
||||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_TL_TL_X_MASK = 0x7FFF;
|
||||
@@ -205,12 +245,21 @@ constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_X_MASK = 0x7FFF;
|
||||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_SHIFT = 16;
|
||||
constexpr uint32_t PA_SC_GENERIC_SCISSOR_BR_BR_Y_MASK = 0x7FFF;
|
||||
|
||||
constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
|
||||
|
||||
constexpr uint32_t CB_BLEND_RED = 0x105;
|
||||
constexpr uint32_t CB_BLEND_GREEN = 0x106;
|
||||
constexpr uint32_t CB_BLEND_BLUE = 0x107;
|
||||
constexpr uint32_t CB_BLEND_ALPHA = 0x108;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_TL = 0x94;
|
||||
constexpr uint32_t PA_SC_VPORT_SCISSOR_0_BR = 0x95;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMIN_0 = 0xB4;
|
||||
constexpr uint32_t PA_SC_VPORT_ZMAX_0 = 0xB5;
|
||||
constexpr uint32_t PA_SC_RIGHT_VERT_GRID = 0xE8;
|
||||
constexpr uint32_t PA_SC_LEFT_VERT_GRID = 0xE9;
|
||||
constexpr uint32_t PA_SC_HORIZ_GRID = 0xEA;
|
||||
constexpr uint32_t PA_SC_FOV_WINDOW_LR = 0xEB;
|
||||
constexpr uint32_t PA_SC_FOV_WINDOW_TB = 0xEC;
|
||||
constexpr uint32_t CB_RMI_GL2_CACHE_CONTROL = 0x104;
|
||||
constexpr uint32_t CB_BLEND_RED = 0x105;
|
||||
constexpr uint32_t CB_BLEND_GREEN = 0x106;
|
||||
constexpr uint32_t CB_BLEND_BLUE = 0x107;
|
||||
constexpr uint32_t CB_BLEND_ALPHA = 0x108;
|
||||
constexpr uint32_t CB_DCC_CONTROL = 0x109;
|
||||
|
||||
constexpr uint32_t DB_STENCIL_CONTROL = 0x10B;
|
||||
constexpr uint32_t DB_STENCIL_CONTROL_STENCILFAIL_SHIFT = 0;
|
||||
@@ -246,9 +295,29 @@ constexpr uint32_t DB_STENCILREFMASK_BF_STENCILWRITEMASK_BF_MASK = 0xFF;
|
||||
constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_SHIFT = 24;
|
||||
constexpr uint32_t DB_STENCILREFMASK_BF_STENCILOPVAL_BF_MASK = 0xFF;
|
||||
|
||||
constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
|
||||
|
||||
constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
|
||||
constexpr uint32_t PA_CL_VPORT_XSCALE = 0x10F;
|
||||
constexpr uint32_t PA_CL_VPORT_XOFFSET = 0x110;
|
||||
constexpr uint32_t PA_CL_VPORT_YSCALE = 0x111;
|
||||
constexpr uint32_t PA_CL_VPORT_YOFFSET = 0x112;
|
||||
constexpr uint32_t PA_CL_VPORT_ZSCALE = 0x113;
|
||||
constexpr uint32_t PA_CL_VPORT_ZOFFSET = 0x114;
|
||||
constexpr uint32_t PA_CL_UCP_0_X = 0x16F;
|
||||
constexpr uint32_t PA_CL_UCP_0_Y = 0x170;
|
||||
constexpr uint32_t PA_CL_UCP_0_Z = 0x171;
|
||||
constexpr uint32_t PA_CL_UCP_0_W = 0x172;
|
||||
constexpr uint32_t SPI_PS_INPUT_CNTL_0 = 0x191;
|
||||
constexpr uint32_t SPI_PS_INPUT_CNTL_31 = 0x1B0;
|
||||
constexpr uint32_t SPI_VS_OUT_CONFIG = 0x1B1;
|
||||
constexpr uint32_t SPI_PS_INPUT_ENA = 0x1B3;
|
||||
constexpr uint32_t SPI_PS_INPUT_ADDR = 0x1B4;
|
||||
constexpr uint32_t SPI_INTERP_CONTROL_0 = 0x1B5;
|
||||
constexpr uint32_t SPI_PS_IN_CONTROL = 0x1B6;
|
||||
constexpr uint32_t SPI_BARYC_CNTL = 0x1B8;
|
||||
constexpr uint32_t SPI_TMPRING_SIZE = 0x1BA;
|
||||
constexpr uint32_t SPI_SHADER_IDX_FORMAT = 0x1C2;
|
||||
constexpr uint32_t SPI_SHADER_POS_FORMAT = 0x1C3;
|
||||
constexpr uint32_t SPI_SHADER_Z_FORMAT = 0x1C4;
|
||||
constexpr uint32_t SPI_SHADER_COL_FORMAT = 0x1C5;
|
||||
|
||||
constexpr uint32_t CB_BLEND0_CONTROL = 0x1E0;
|
||||
constexpr uint32_t CB_BLEND0_CONTROL_COLOR_SRCBLEND_SHIFT = 0;
|
||||
@@ -268,6 +337,8 @@ constexpr uint32_t CB_BLEND0_CONTROL_SEPARATE_ALPHA_BLEND_MASK = 0x1;
|
||||
constexpr uint32_t CB_BLEND0_CONTROL_ENABLE_SHIFT = 30;
|
||||
constexpr uint32_t CB_BLEND0_CONTROL_ENABLE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t GE_MAX_OUTPUT_PER_SUBGROUP = 0x1FF;
|
||||
|
||||
constexpr uint32_t DB_DEPTH_CONTROL = 0x200;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_SHIFT = 0;
|
||||
constexpr uint32_t DB_DEPTH_CONTROL_STENCIL_ENABLE_MASK = 0x1;
|
||||
@@ -304,12 +375,56 @@ constexpr uint32_t DB_EQAA_INTERPOLATE_COMP_Z_MASK = 0x1;
|
||||
constexpr uint32_t DB_EQAA_STATIC_ANCHOR_ASSOCIATIONS_SHIFT = 20;
|
||||
constexpr uint32_t DB_EQAA_STATIC_ANCHOR_ASSOCIATIONS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t DB_SHADER_CONTROL = 0x203;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_Z_EXPORT_ENABLE_SHIFT = 0;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_Z_EXPORT_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_Z_ORDER_SHIFT = 4;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_Z_ORDER_MASK = 0x3;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_KILL_ENABLE_SHIFT = 6;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_KILL_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_EXEC_ON_NOOP_SHIFT = 10;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_EXEC_ON_NOOP_MASK = 0x1;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_CONSERVATIVE_Z_EXPORT_SHIFT = 13;
|
||||
constexpr uint32_t DB_SHADER_CONTROL_CONSERVATIVE_Z_EXPORT_MASK = 0x3;
|
||||
|
||||
constexpr uint32_t CB_COLOR_CONTROL = 0x202;
|
||||
constexpr uint32_t CB_COLOR_CONTROL_MODE_SHIFT = 4;
|
||||
constexpr uint32_t CB_COLOR_CONTROL_MODE_MASK = 0x7;
|
||||
constexpr uint32_t CB_COLOR_CONTROL_ROP3_SHIFT = 16;
|
||||
constexpr uint32_t CB_COLOR_CONTROL_ROP3_MASK = 0xFF;
|
||||
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL = 0x204;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_UCP_ENA_SHIFT = 0;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_UCP_ENA_MASK = 0x3F;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_Y_SCALE_NEG_SHIFT = 13;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_Y_SCALE_NEG_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_MODE_SHIFT = 14;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_PS_UCP_MODE_MASK = 0x3;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_CLIP_DISABLE_SHIFT = 16;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_CLIP_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_UCP_CULL_ONLY_ENA_SHIFT = 17;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_UCP_CULL_ONLY_ENA_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_SHIFT = 18;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_SHIFT = 19;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_SHIFT = 20;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_VTX_KILL_OR_SHIFT = 21;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_VTX_KILL_OR_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DX_RASTERIZATION_KILL_SHIFT = 22;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DX_RASTERIZATION_KILL_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DX_LINEAR_ATTR_CLIP_ENA_SHIFT = 24;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_DX_LINEAR_ATTR_CLIP_ENA_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_VTE_VPORT_PROVOKE_DISABLE_SHIFT = 25;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_VTE_VPORT_PROVOKE_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_NEAR_DISABLE_SHIFT = 26;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_NEAR_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_FAR_DISABLE_SHIFT = 27;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_FAR_DISABLE_MASK = 0x1;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_PROG_NEAR_ENA_SHIFT = 28;
|
||||
constexpr uint32_t PA_CL_CLIP_CNTL_ZCLIP_PROG_NEAR_ENA_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL = 0x205;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_CULL_FRONT_SHIFT = 0;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_CULL_FRONT_MASK = 0x1;
|
||||
@@ -334,10 +449,21 @@ constexpr uint32_t PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST_MASK = 0x1;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_SHIFT = 20;
|
||||
constexpr uint32_t PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t PA_CL_VTE_CNTL = 0x206;
|
||||
constexpr uint32_t PA_CL_VS_OUT_CNTL = 0x207;
|
||||
constexpr uint32_t PA_SU_SMALL_PRIM_FILTER_CNTL = 0x20C;
|
||||
constexpr uint32_t PA_CL_OBJPRIM_ID_CNTL = 0x20D;
|
||||
constexpr uint32_t PA_STEREO_CNTL = 0x210;
|
||||
constexpr uint32_t PA_STATE_STEREO_X = 0x211;
|
||||
constexpr uint32_t PA_SU_POINT_SIZE = 0x280;
|
||||
constexpr uint32_t PA_SU_POINT_MINMAX = 0x281;
|
||||
|
||||
constexpr uint32_t PA_SU_LINE_CNTL = 0x282;
|
||||
constexpr uint32_t PA_SU_LINE_CNTL_WIDTH_SHIFT = 0;
|
||||
constexpr uint32_t PA_SU_LINE_CNTL_WIDTH_MASK = 0xFFFF;
|
||||
|
||||
constexpr uint32_t VGT_GS_ONCHIP_CNTL = 0x291;
|
||||
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0 = 0x292;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_MSAA_ENABLE_SHIFT = 0;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_MSAA_ENABLE_MASK = 0x1;
|
||||
@@ -346,7 +472,13 @@ constexpr uint32_t PA_SC_MODE_CNTL_0_VPORT_SCISSOR_ENABLE_MASK = 0x1;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_LINE_STIPPLE_ENABLE_SHIFT = 2;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_0_LINE_STIPPLE_ENABLE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t VGT_GS_OUT_PRIM_TYPE = 0x29B;
|
||||
constexpr uint32_t PA_SC_MODE_CNTL_1 = 0x293;
|
||||
constexpr uint32_t VGT_GS_OUT_PRIM_TYPE = 0x29B;
|
||||
constexpr uint32_t VGT_PRIMITIVEID_EN = 0x2A1;
|
||||
constexpr uint32_t VGT_PRIMITIVEID_RESET = 0x2A3;
|
||||
constexpr uint32_t VGT_DRAW_PAYLOAD_CNTL = 0x2A6;
|
||||
constexpr uint32_t VGT_ESGS_RING_ITEMSIZE = 0x2AB;
|
||||
constexpr uint32_t VGT_REUSE_OFF = 0x2AD;
|
||||
|
||||
constexpr uint32_t DB_HTILE_SURFACE = 0x2AF;
|
||||
constexpr uint32_t DB_HTILE_SURFACE_LINEAR_SHIFT = 0;
|
||||
@@ -364,9 +496,24 @@ constexpr uint32_t DB_HTILE_SURFACE_PREFETCH_HEIGHT_MASK = 0x3F;
|
||||
constexpr uint32_t DB_HTILE_SURFACE_DST_OUTSIDE_ZERO_TO_ONE_SHIFT = 16;
|
||||
constexpr uint32_t DB_HTILE_SURFACE_DST_OUTSIDE_ZERO_TO_ONE_MASK = 0x1;
|
||||
|
||||
constexpr uint32_t VGT_SHADER_STAGES_EN = 0x2D5;
|
||||
|
||||
constexpr uint32_t PA_SC_CENTROID_PRIORITY_0 = 0x2F5;
|
||||
constexpr uint32_t DB_SRESULTS_COMPARE_STATE0 = 0x2B0;
|
||||
constexpr uint32_t DB_SRESULTS_COMPARE_STATE1 = 0x2B1;
|
||||
constexpr uint32_t VGT_GS_MAX_VERT_OUT = 0x2CE;
|
||||
constexpr uint32_t GE_NGG_SUBGRP_CNTL = 0x2D3;
|
||||
constexpr uint32_t VGT_TESS_DISTRIBUTION = 0x2D4;
|
||||
constexpr uint32_t VGT_SHADER_STAGES_EN = 0x2D5;
|
||||
constexpr uint32_t VGT_LS_HS_CONFIG = 0x2D6;
|
||||
constexpr uint32_t VGT_TF_PARAM = 0x2DB;
|
||||
constexpr uint32_t DB_ALPHA_TO_MASK = 0x2DC;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_DB_FMT_CNTL = 0x2DE;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_CLAMP = 0x2DF;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_FRONT_SCALE = 0x2E0;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_FRONT_OFFSET = 0x2E1;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_BACK_SCALE = 0x2E2;
|
||||
constexpr uint32_t PA_SU_POLY_OFFSET_BACK_OFFSET = 0x2E3;
|
||||
constexpr uint32_t VGT_GS_INSTANCE_CNT = 0x2E4;
|
||||
constexpr uint32_t PA_SC_CENTROID_PRIORITY_0 = 0x2F5;
|
||||
constexpr uint32_t PA_SC_CENTROID_PRIORITY_1 = 0x2F6;
|
||||
|
||||
constexpr uint32_t PA_SC_AA_CONFIG = 0x2F8;
|
||||
constexpr uint32_t PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES_SHIFT = 0;
|
||||
@@ -378,24 +525,52 @@ constexpr uint32_t PA_SC_AA_CONFIG_MAX_SAMPLE_DIST_MASK = 0xF;
|
||||
constexpr uint32_t PA_SC_AA_CONFIG_MSAA_EXPOSED_SAMPLES_SHIFT = 20;
|
||||
constexpr uint32_t PA_SC_AA_CONFIG_MSAA_EXPOSED_SAMPLES_MASK = 0x7;
|
||||
|
||||
constexpr uint32_t PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x2FE;
|
||||
constexpr uint32_t PA_SU_VTX_CNTL = 0x2F9;
|
||||
constexpr uint32_t PA_CL_GB_VERT_CLIP_ADJ = 0x2FA;
|
||||
constexpr uint32_t PA_CL_GB_VERT_DISC_ADJ = 0x2FB;
|
||||
constexpr uint32_t PA_CL_GB_HORZ_CLIP_ADJ = 0x2FC;
|
||||
constexpr uint32_t PA_CL_GB_HORZ_DISC_ADJ = 0x2FD;
|
||||
constexpr uint32_t PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 = 0x2FE;
|
||||
constexpr uint32_t PA_SC_AA_MASK_X0Y0_X1Y0 = 0x30E;
|
||||
constexpr uint32_t PA_SC_AA_MASK_X0Y1_X1Y1 = 0x30F;
|
||||
constexpr uint32_t PA_SC_SHADER_CONTROL = 0x310;
|
||||
constexpr uint32_t PA_SC_BINNER_CNTL_0 = 0x311;
|
||||
constexpr uint32_t PA_SC_BINNER_CNTL_1 = 0x312;
|
||||
constexpr uint32_t PA_SC_CONSERVATIVE_RASTERIZATION_CNTL = 0x313;
|
||||
constexpr uint32_t PA_SC_NGG_MODE_CNTL = 0x314;
|
||||
constexpr uint32_t CB_COLOR0_BASE = 0x318;
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
|
||||
constexpr uint32_t CB_COLOR0_BASE = 0x318;
|
||||
constexpr uint32_t CB_COLOR0_VIEW = 0x31B;
|
||||
constexpr uint32_t CB_COLOR0_INFO = 0x31C;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB = 0x31D;
|
||||
constexpr uint32_t CB_COLOR0_DCC_CONTROL = 0x31E;
|
||||
constexpr uint32_t CB_COLOR0_CMASK = 0x31F;
|
||||
constexpr uint32_t CB_COLOR0_FMASK = 0x321;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD0 = 0x323;
|
||||
constexpr uint32_t CB_COLOR0_CLEAR_WORD1 = 0x324;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE = 0x325;
|
||||
constexpr uint32_t CB_COLOR0_BASE_EXT = 0x390;
|
||||
constexpr uint32_t CB_COLOR0_CMASK_BASE_EXT = 0x398;
|
||||
constexpr uint32_t CB_COLOR0_FMASK_BASE_EXT = 0x3A0;
|
||||
constexpr uint32_t CB_COLOR0_DCC_BASE_EXT = 0x3A8;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB2 = 0x3B0;
|
||||
constexpr uint32_t CB_COLOR0_ATTRIB3 = 0x3B8;
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
constexpr uint32_t FSR_RECURSIONS0 = 0x800003FC;
|
||||
constexpr uint32_t FSR_RECURSIONS1 = 0x800003FD;
|
||||
constexpr uint32_t PA_SC_FSR_ENABLE = 0x800003FE;
|
||||
constexpr uint32_t CX_NOP = 0x800003FF;
|
||||
|
||||
constexpr uint32_t CX_NUM = 0x3FF + 1;
|
||||
|
||||
/* Shader registers */
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC4_PS = 0x1;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_PS = 0x6;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_PS = 0x7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_PS = 0x8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_PS = 0x9;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS = 0xA;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_PS_VGPRS_SHIFT = 0;
|
||||
@@ -411,11 +586,42 @@ constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_USER_SGPR_MASK = 0x1F;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_SHIFT = 7;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_PS_WAVE_CNT_EN_MASK = 0x0;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_0 = 0x4C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_15 = 0x5B;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_0 = 0xC;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_PS_15 = 0x1B;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_PS_0 = 0x32;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_0 = 0x4C;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_VS_15 = 0x5B;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_GS = 0x80;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC4_GS = 0x81;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_GS = 0x82;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_GS = 0x83;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_GS = 0x87;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_GS = 0x88;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_GS = 0x89;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_GS = 0x8A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_GS = 0x8B;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_GS_0 = 0x8C;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_ESGS_0 = 0xB2;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_ES = 0xC8;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_ES = 0xC9;
|
||||
constexpr uint32_t SPI_SHADER_PGM_CHKSUM_HS = 0x100;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC4_HS = 0x101;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_LO_HS = 0x102;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_ADDR_HI_HS = 0x103;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC3_HS = 0x107;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_HS = 0x108;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_HS = 0x109;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC1_HS = 0x10A;
|
||||
constexpr uint32_t SPI_SHADER_PGM_RSRC2_HS = 0x10B;
|
||||
constexpr uint32_t SPI_SHADER_USER_DATA_HS_0 = 0x10C;
|
||||
constexpr uint32_t SPI_SHADER_USER_ACCUM_LSHS_0 = 0x132;
|
||||
constexpr uint32_t SPI_SHADER_PGM_LO_LS = 0x148;
|
||||
constexpr uint32_t SPI_SHADER_PGM_HI_LS = 0x149;
|
||||
constexpr uint32_t COMPUTE_START_X = 0x204;
|
||||
constexpr uint32_t COMPUTE_START_Y = 0x205;
|
||||
constexpr uint32_t COMPUTE_START_Z = 0x206;
|
||||
constexpr uint32_t COMPUTE_PGM_LO = 0x20C;
|
||||
constexpr uint32_t COMPUTE_PGM_HI = 0x20D;
|
||||
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC1 = 0x212;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC1_VGPRS_SHIFT = 0;
|
||||
@@ -443,14 +649,62 @@ constexpr uint32_t COMPUTE_PGM_RSRC2_TIDIG_COMP_CNT_MASK = 0x3;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC2_LDS_SIZE_SHIFT = 15;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC2_LDS_SIZE_MASK = 0x1FF;
|
||||
|
||||
constexpr uint32_t COMPUTE_USER_DATA_0 = 0x240;
|
||||
constexpr uint32_t COMPUTE_USER_DATA_15 = 0x24F;
|
||||
constexpr uint32_t COMPUTE_RESOURCE_LIMITS = 0x215;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE0 = 0x216;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE1 = 0x217;
|
||||
constexpr uint32_t COMPUTE_TMPRING_SIZE = 0x218;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE2 = 0x219;
|
||||
constexpr uint32_t COMPUTE_DESTINATION_EN_SE3 = 0x21A;
|
||||
constexpr uint32_t COMPUTE_USER_ACCUM_0 = 0x224;
|
||||
constexpr uint32_t COMPUTE_PGM_RSRC3 = 0x228;
|
||||
constexpr uint32_t COMPUTE_SHADER_CHKSUM = 0x22A;
|
||||
constexpr uint32_t COMPUTE_USER_DATA_0 = 0x240;
|
||||
constexpr uint32_t COMPUTE_USER_DATA_15 = 0x24F;
|
||||
constexpr uint32_t COMPUTE_DISPATCH_TUNNEL = 0x27D;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
constexpr uint32_t SH_NOP = 0x800002FF;
|
||||
|
||||
constexpr uint32_t SH_NUM = 0x2FF + 1;
|
||||
|
||||
/* User config registers */
|
||||
|
||||
constexpr uint32_t GE_CNTL = 0x25b;
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_PRIMITIVE_TYPE = 0x242;
|
||||
constexpr uint32_t VGT_OBJECT_ID = 0x248;
|
||||
constexpr uint32_t GE_INDX_OFFSET = 0x24A;
|
||||
constexpr uint32_t GE_MULTI_PRIM_IB_RESET_EN = 0x24B;
|
||||
constexpr uint32_t VGT_HS_OFFCHIP_PARAM = 0x24F;
|
||||
constexpr uint32_t VGT_TF_MEMORY_BASE = 0x250;
|
||||
constexpr uint32_t GE_CNTL = 0x25B;
|
||||
constexpr uint32_t GE_USER_VGPR1 = 0x25C;
|
||||
constexpr uint32_t GE_USER_VGPR2 = 0x25D;
|
||||
constexpr uint32_t GE_USER_VGPR3 = 0x25E;
|
||||
constexpr uint32_t GE_STEREO_CNTL = 0x25F;
|
||||
constexpr uint32_t GE_USER_VGPR_EN = 0x262;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR = 0x380;
|
||||
constexpr uint32_t TA_CS_BC_BASE_ADDR_HI = 0x381;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_FACTORS = 0x382;
|
||||
constexpr uint32_t GDS_OA_CNTL = 0x41D;
|
||||
constexpr uint32_t GDS_OA_COUNTER = 0x41E;
|
||||
constexpr uint32_t GDS_OA_ADDRESS = 0x41F;
|
||||
|
||||
/* Fake codes. Don't exist on real HW */
|
||||
|
||||
constexpr uint32_t FSR_EXTEND_SUBPIXEL_ROUNDING = 0x80003FF4;
|
||||
constexpr uint32_t FSR_ALPHA_VALUE0 = 0x80003FF5;
|
||||
constexpr uint32_t FSR_ALPHA_VALUE1 = 0x80003FF6;
|
||||
constexpr uint32_t FSR_CONTROL_POINT0 = 0x80003FF7;
|
||||
constexpr uint32_t FSR_CONTROL_POINT1 = 0x80003FF8;
|
||||
constexpr uint32_t FSR_CONTROL_POINT2 = 0x80003FF9;
|
||||
constexpr uint32_t FSR_CONTROL_POINT3 = 0x80003FFA;
|
||||
constexpr uint32_t FSR_WINDOW0 = 0x80003FFB;
|
||||
constexpr uint32_t FSR_WINDOW1 = 0x80003FFC;
|
||||
constexpr uint32_t TEXTURE_GRADIENT_CONTROL = 0x80003FFD;
|
||||
constexpr uint32_t MEMORY_MAPPING_MASK = 0x80003FFE;
|
||||
constexpr uint32_t UC_NOP = 0x80003FFF;
|
||||
|
||||
constexpr uint32_t UC_NUM = 0x3FFF + 1;
|
||||
|
||||
void DumpPm4PacketStream(Core::File* file, uint32_t* cmd_buffer, uint32_t start_dw, uint32_t num_dw);
|
||||
|
||||
|
||||
@@ -17,6 +17,7 @@ namespace HW {
|
||||
struct VertexShaderInfo;
|
||||
struct PixelShaderInfo;
|
||||
struct ComputeShaderInfo;
|
||||
struct ShaderRegisters;
|
||||
} // namespace HW
|
||||
|
||||
enum class ShaderType
|
||||
@@ -802,18 +803,19 @@ struct ShaderPixelInputInfo
|
||||
};
|
||||
|
||||
void ShaderCalcBindingIndices(ShaderBindResources* bind);
|
||||
void ShaderGetInputInfoVS(const HW::VertexShaderInfo* regs, ShaderVertexInputInfo* info);
|
||||
void ShaderGetInputInfoPS(const HW::PixelShaderInfo* regs, const ShaderVertexInputInfo* vs_info, ShaderPixelInputInfo* ps_info);
|
||||
void ShaderGetInputInfoCS(const HW::ComputeShaderInfo* regs, ShaderComputeInputInfo* info);
|
||||
void ShaderGetInputInfoVS(const HW::VertexShaderInfo* regs, const HW::ShaderRegisters* sh, ShaderVertexInputInfo* info);
|
||||
void ShaderGetInputInfoPS(const HW::PixelShaderInfo* regs, const HW::ShaderRegisters* sh, const ShaderVertexInputInfo* vs_info,
|
||||
ShaderPixelInputInfo* ps_info);
|
||||
void ShaderGetInputInfoCS(const HW::ComputeShaderInfo* regs, const HW::ShaderRegisters* sh, ShaderComputeInputInfo* info);
|
||||
void ShaderDbgDumpInputInfo(const ShaderVertexInputInfo* info);
|
||||
void ShaderDbgDumpInputInfo(const ShaderPixelInputInfo* info);
|
||||
void ShaderDbgDumpInputInfo(const ShaderComputeInputInfo* info);
|
||||
ShaderId ShaderGetIdVS(const HW::VertexShaderInfo* regs, const ShaderVertexInputInfo* input_info);
|
||||
ShaderId ShaderGetIdPS(const HW::PixelShaderInfo* regs, const ShaderPixelInputInfo* input_info);
|
||||
ShaderId ShaderGetIdCS(const HW::ComputeShaderInfo* regs, const ShaderComputeInputInfo* input_info);
|
||||
ShaderCode ShaderParseVS(const HW::VertexShaderInfo* regs);
|
||||
ShaderCode ShaderParsePS(const HW::PixelShaderInfo* regs);
|
||||
ShaderCode ShaderParseCS(const HW::ComputeShaderInfo* regs);
|
||||
ShaderCode ShaderParseVS(const HW::VertexShaderInfo* regs, const HW::ShaderRegisters* sh);
|
||||
ShaderCode ShaderParsePS(const HW::PixelShaderInfo* regs, const HW::ShaderRegisters* sh);
|
||||
ShaderCode ShaderParseCS(const HW::ComputeShaderInfo* regs, const HW::ShaderRegisters* sh);
|
||||
// ShaderBindParameters ShaderGetBindParametersVS(const ShaderCode& code, const ShaderVertexInputInfo* input_info);
|
||||
// ShaderBindParameters ShaderGetBindParametersPS(const ShaderCode& code, const ShaderPixelInputInfo* input_info);
|
||||
// ShaderBindParameters ShaderGetBindParametersCS(const ShaderCode& code, const ShaderComputeInputInfo* input_info);
|
||||
|
||||
Reference in New Issue
Block a user